Ara es mostren els items 1-15 de 15

    • Accurate off-line phase classification for HW/SW co-designed processors 

      Brankovic, Aleksandar; Stavrou, Kyriakos; Gibert Codina, Enric; González Colás, Antonio María (Association for Computing Machinery (ACM), 2014)
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      Evaluation techniques in microprocessor design are mostly based on simulating selected application's samples using a cycle-accurate simulator. These samples usually correspond to different phases of the application stream. ...
    • Analysis of CPI variance for dynamic binary translators/optimizers modules 

      Brankovic, Aleksandar; Stavrou, Kyriakos; Gibert Codina, Enric; González Colás, Antonio María (IEEE, 2012)
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      Dynamic Binary Translators and Optimizers (DBTOs) have been established as a hot research topic. They are used in many different systems, such as emulation, instrumentation tools and innovative HW/SW co-designed ...
    • Anaphase: a fine-grain thread decomposition scheme for speculative multithreading 

      Madriles Gimeno, Carles; López Muñoz, Pedro; Codina Viñas, Josep M.; Gibert Codina, Enric; Latorre Salinas, Fernando; Martínez Vicente, Alejandro; Martinez, Raul; González Colás, Antonio María (IEEE Computer Society, 2009)
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      Industry is moving towards multi-core designs as we have hit the memory and power walls. Multi-core designs are very effective to exploit thread-level parallelism (TLP) but do not provide benefits when executing serial ...
    • Boosting single-thread performance in multi-core systems through fine-grain multi-threading 

      Madriles Gimeno, Carles; López Muñoz, Pedro; Codina Viñas, Josep M.; Gibert Codina, Enric; Latorre Salinas, Fernando; Martínez Vicente, Alejandro; Martinez Morais, Raul; González Colás, Antonio María (ACM Press. Association for Computing Machinery, 2009-06)
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      Industry has shifted towards multi-core designs as we have hit the memory and power walls. However, single thread performance remains of paramount importance since some applications have limited thread-level parallelism ...
    • DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support 

      Pavlou, Demos; Gibert Codina, Enric; Latorre, Fernando; González Colás, Antonio María (2012)
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      Dynamic Binary Translators (DBT) and Dynamic Binary Opti- mization (DBO) by software are used widely for several reasons including performance, design simplification and virtualization. However, the software layer in ...
    • Distributed data cache designs for clustered VLIW processors 

      Gibert Codina, Enric; Sánchez, Jesús; González Colás, Antonio María (2005-10)
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      Wire delays are a major concern for current and forthcoming processors. One approach to deal with this problem is to divide the processor into semi-independent units referred to as clusters. A cluster usually consists of ...
    • Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor 

      Gibert Codina, Enric; Sánchez Navarro, Jesús; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2002)
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      Clustering is a common technique to overcome the wire delay problem incurred by the evolution of technology. Fully-distributed architectures, where the register file, the functional units and the data cache are partitioned, ...
    • Flexible compiler-managed L0 buffers for clustered VLIW processors 

      Gibert Codina, Enric; Sánchez Navarro, F. Jesús; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2003)
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      Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as clusters. A cluster usually consists of a ...
    • Global productiveness propagation: A code optimization technique to speculatively prune useless narrow computations 

      Bhagat, Indu; Gibert Codina, Enric; Sanchez, Jesus; González Colás, Antonio María (ACM Press, NY, 2011)
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      This paper proposes a unique hardware-software collaborative strategy to remove useless work at 16-bit data-width granularity. The underlying motivation is to design a low power execution platform by exploiting ‘narrow’ ...
    • HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation 

      Kumar, Rakesh; Cano, José; Brankovic, Aleksandar; Pavlou, Demos; Stavrou, Kyriakos; Gibert Codina, Enric; Martínez, Alejandro; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2017)
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      Improving single thread performance is a key challenge in modern microprocessors especially because the traditional approach of increasing clock frequency and deep pipelining cannot be pushed further due to power constraints. ...
    • Local scheduling techniques for memory coherence in a clustered VLIW processor with a distributed data cache 

      Gibert Codina, Enric; Sánchez, Jesús; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2003)
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      Clustering is a common technique to deal with wire delays. Fully-distributed architectures, where the register file, the functional units and the cache memory are partitioned, are particularly effective to deal with these ...
    • Performance analysis and predictability of the software layer in Dynamic Binary Translators/Optimizers 

      Brankovic, Aleksandar; Stavrou, K.; Gibert Codina, Enric; Gonzalez, Antonio (ACM, 2013)
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      Dynamic Binary Translators and Optimizers (DBTOs) have been established as a common architecture during the last years. They are used in many different systems, such as emulation, instrumentation tools and innovative HW/SW ...
    • Quantitative characterization of the software layer of a HW/SW co-designed processor 

      Cano Reyes, José; Kumar, Rakesh; Brankovic, Aleksandar; Pavlou, Demos; Stavrou, Kyriakos; Gibert Codina, Enric; Martínez, Alejandro; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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      HW/SW co-designed processors currently have a renewed interest due to their capability to boost performance without running into the power and complexity walls. By employing a software layer that performs dynamic binary ...
    • Variable-based multi-module data caches for clustered VLIW processors 

      Gibert Codina, Enric; Abella Ferrer, Jaume; Sánchez Navarro, Jesús; Vera Rivera, Francisco Javier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2005)
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      Memory structures consume an important fraction of the total processor energy. One solution to reduce the energy consumed by cache memories consists of reducing their supply voltage and/or increase their threshold voltage ...
    • Warm-up simulation methodology for HW/SW co-designed processors 

      Brankovic, Aleksandar; Stavrou, K.; Gibert Codina, Enric; González Colás, Antonio María (ACM, 2014)
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      Evaluation techniques in microprocessor design are mostly based on simulating selected application samples using a cycle-accurate simulator. In order to achieve accurate results, microarchitectural structures are warmed-up ...