Exploració per autor "Parcerisa Bundó, Joan Manuel"
Ara es mostren els items 1-20 de 31
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A cost-effective clustered architecture
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Text en actes de congrés
Accés obertIn current superscalar processors, all floating-point resources are idle during the execution of integer programs. As previous works show, this problem can be alleviated if the floating-point cluster is extended to execute ... -
An energy-efficient memory unit for clustered microarchitectures
(2016-08-01)
Article
Accés obertWhereas clustered microarchitectures themselves have been extensively studied, the memory units for these clustered microarchitectures have received relatively little attention. This article discusses some of the inherent ... -
Boustrophedonic frames: Quasi-optimal L2 caching for textures in GPUs
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Text en actes de congrés
Accés obertLiterature is plentiful in works exploiting cache locality for GPUs. A majority of them explore replacement or bypassing policies. In this paper, however, we surpass this exploration by fabricating a formal proof for a ... -
Design of Clustered Superscalar Microarchitectures
(Universitat Politècnica de Catalunya, 2004-06-17)
Tesi
Accés obertL'objectiu d'aquesta tesi és proposar noves tècniques per al disseny de microarquitectures clúster superescalars eficients. Les microarquitectures clúster particionen el disseny de diversos components crítics del hardware ... -
DTexL: Decoupled raster pipeline for texture locality
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertContemporary GPU architectures have multiple shader cores and a scheduler that distributes work (threads) among them, focusing on load balancing. These load balancing techniques favor thread distributions that are detrimental ... -
DTM-NUCA: dynamic texture mapping-NUCA for energy-efficient graphics rendering
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertModern mobile GPUs integrate an increasing number of shader cores to speedup the execution of graphics workloads. Each core integrates a private Texture Cache to apply texturing effects on objects, which is backed-up by a ... -
Dynamic cluster assignment mechanisms
(Institute of Electrical and Electronics Engineers (IEEE), 2000)
Text en actes de congrés
Accés obertClustered microarchitectures are an effective approach to reducing the penalties caused by wire delays inside a chip. Current superscalar processors have in fact a two-cluster microarchitecture with a naive code partitioning ... -
Dynamic sampling rate: harnessing frame coherence in graphics applications for energy-efficient GPUs
(Springer Nature, 2022)
Article
Accés obertIn real-time rendering, a 3D scene is modelled with meshes of triangles that the GPU projects to the screen. They are discretized by sampling each triangle at regular space intervals to generate fragments which are then ... -
Early register release for out-of-order processors with register windows
(Institute of Electrical and Electronics Engineers (IEEE), 2007)
Text en actes de congrés
Accés obertRegister windows is an architectural technique that reduces memory operations required to save and restore registers across procedure calls. Its effectiveness depends on the size of the register file. Such register ... -
Early visibility resolution for removing ineffectual computations in the graphics pipeline
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Text en actes de congrés
Accés restringit per política de l'editorialGPUs' main workload is real-time image rendering. These applications take a description of a (animated) scene and produce the corresponding image(s). An image is rendered by computing the colors of all its pixels. It is ... -
Efficient interconnects for clustered microarchitectures
(Institute of Electrical and Electronics Engineers (IEEE), 2002)
Text en actes de congrés
Accés obertClustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we investigate the design of on-chip interconnection ... -
Eliminating redundant fragment shader executions on a mobile GPU via hardware memoization
(2014)
Text en actes de congrés
Accés restringit per política de l'editorialRedundancy is at the heart of graphical applications. In fact, generating an animation typically involves the succession of extremely similar images. In terms of rendering these images, this behavior translates into the ... -
Improving branch prediction and predicated execution in out-of-order processors
(Institute of Electrical and Electronics Engineers (IEEE), 2007)
Text en actes de congrés
Accés obertIf-conversion is a compiler technique that reduces the misprediction penalties caused by hard-to-predict branches, transforming control dependencies into data dependencies. Although it is globally beneficial, it has a ... -
Improving latency tolerance of multithreading through decoupling
(2001-10)
Article
Accés obertThe increasing hardware complexity of dynamically scheduled superscalar processors may compromise the scalability of this organization to make an efficient use of future increases in transistor budget. SMT processors, ... -
Improving the energy efficiency of the graphics pipeline by reducing overshading
(2021)
Text en actes de congrés
Accés obertThe most common task of GPUs is to render images in real time. When rendering a 3D scene, a key step is determining which parts of every object are visible in the final image. There are different approaches to solve the ... -
La Influencia del orden de las preguntas en los exámenes de primer curso
(Universitat Jaume I. Escola Superior de Tecnologia i Ciències Experimentals, 2013-07-10)
Text en actes de congrés
Accés obertEl orden de las preguntas en un examen no debería tener influencia en sus resultados. Sin embargo, los autores tenemos la sensación de que los estudiantes de primero suelen ser secuenciales a la hora de resolver los ... -
Leveraging register windows to reduce physical registers to the bare minimum
(2010-12)
Article
Accés obertRegister window is an architectural technique that reduces memory operations required to save and restore registers across procedure calls. Its effectiveness depends on the size of the register file. Such register requirements ... -
Memory bank predictors
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés obertCache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access can help to improve the performance in ... -
Omega-Test: A predictive early-Z culling to improve the graphics pipeline energy-efficiency
(2022-12-01)
Article
Accés obertThe most common task of GPUs is to render images in real time. When rendering a 3D scene, a key step is to determine which parts of every object are visible in the final image. There are different approaches to solve the ... -
On-chip interconnects and instruction steering schemes for clustered microarchitectures
(2005-02)
Article
Accés obertClustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we investigate the design of on-chip interconnection ...
