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Vista preliminarDataTítolAutor(s)
2013A cache design for probabilistically analysable real-time systemsKosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier
An analyzable memory controller ....pdf.jpg5-feb-2010An analyzable memory controller for hard real-time CMPsPaolieri, Marco; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo
2013Applying measurement-based probabilistic timing analysis to buffer resourcesKosmidis, Leonidas; Vardanega, Tulio; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier
2014Bus designs for time-probabilistic multicore processorsJalle Ibarra, Javier; Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier
2009Characterizing the resource-sharing levels of the UltraSparc T2 processorCakarevic, Vladimir; Radojkovic, Petar; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo
2014Containing timing-related certification cost in automotive systems deploying complex hardwareKosmidis, Leonidas; Quiñones Moreno, Eduardo; Abella Ferrer, Jaume; Farrall, Glenn; Wartel, Franck; Cazorla Almeida, Francisco Javier
2013Deconstructing bus access control policies for real-time multicoresJalle Ibarra, Javier; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier
2013DTM: degraded test mode for fault-aware probabilistic timing analysisSlijepcevic, Mladen; Kosmidis, Leonidas; Abella, Jaume; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier
Castillo.pdf.jpgjun-2008Evolutionary system for prediction and optimization of hardware architecture performanceCastillo, Pedro Angel; Merelo, Juan Julián; Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo; Mora, Antonio; Laredo, Juan Luís; McKee, Sally
Luque.pdf.jpg2010ITCA: Inter-Task Conflict-Aware CPU accounting for CMPLuque, Carlos; Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Valero Cortés, Mateo
2009ITCA: inter-task conflict-aware CPU accounting for CMPsLuque, Carlos; Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Buyuktosunoglu, Alper; Valero Cortés, Mateo
2012Measurement-based probabilistic timing analysis for multi-path programsCucu Grosjean, Liliana; Santinelli, Luca; Houston, Michael; Lo, Code; Vardanega, Tulio; Kosmidis, Leonidas; Abella Ferrer, Jaume; Mezzetti, Enrico; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier
2013Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case studyWartel, Franck; Kosmidis, Leonidas; Lo, Code; Triquet, Benoit; Quiñones Moreno, Eduardo; Abella Ferrer, Jaume; Gogonel, Adriana; Baldovin, Andrea; Mezzetti, Enrico; Cucu Grosjean, Liliana; Vardanega, Tulio; Cazorla Almeida, Francisco Javier
Radojkovic.pdf.jpg2008Measuring operating system overhead on CMT processorsRadojkovic, Petar; Cakarevic, Vladimir; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Gioiosa, Roberto; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo
OSOverhead.pdf.jpgjun-2009Measuring operating system overhead on Sun UltraSparc T1 processorRadojkovic, Petar; Cakarevic, Vladimir; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Gioiosa, Roberto; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo
04625847.pdf.jpg2008MFLUSH: handling long-latency loads in SMT on-chip multiprocessorsAcosta Ojeda, Carmelo Alexis; Cazorla Almeida, Francisco Javier; Ramírez Bellido, Alejandro; Valero Cortés, Mateo
2013Multi-level unified caches for probabilistically time analysable real-time systemsKosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier
SpinLock-CaneraReady-HIPEAC.pdf.jpg4-jun-2008Overhead of the spin-lock loop in UltraSPARC T2Cakarevic, Vladimir; Radojkovic, Petar; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Nemirovsky, Mario; Valero Cortés, Mateo; Pajuelo González, Manuel Alejandro; Verdú Mulà, Javier
2013Probabilistic timing analysis on conventional cache designsKosmidis, Leonidas; Curtsinger, Charlie; Quiñones Moreno, Eduardo; Abella Ferrer, Jaume; Berger, Emery D.; Cazorla Almeida, Francisco Javier
2011RVC: A mechanism for time-analyzable real-time processors with faulty cachesAbella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Sazeides, Yanos; Valero Cortés, Mateo
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