E-prints UPC >

Llistant per Autor Valero Cortés, Mateo

Vista preliminar	Data	Títol	Autor(s)
	2012	ADAM : an efficient data management mechanism for hybrid high and ultra-low voltage operation caches	Maric, Bojan; Abella Ferrer, Jaume; Valero Cortés, Mateo
	jun-1987	A discrete optimization problem in local networks and data alignment	Fiol Mora, Miquel Àngel; Andrés Yebra, José Luis; Alegre de Miguel, Ignacio; Valero Cortés, Mateo
	21-set-2009	A highly scalable parallel implementation of H.264	Azevedo, Arnaldo; Juurlink, Ben; Meenderinck, Cor; Terechko, Andrei; Hoogerbrugge, Jan; Álvarez Mesa, Mauricio; Ramírez Bellido, Alejandro; Valero Cortés, Mateo
	2011	An abstraction methodology for the evaluation of multi-core multi-threaded architectures	Zilan, Ruken; Verdú Mulà, Javier; García Vidal, Jorge; Nemirovsky, Mario; Milito, Rodolfo; Valero Cortés, Mateo
	5-feb-2010	An analyzable memory controller for hard real-time CMPs	Paolieri, Marco; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo
	2009	Atomic quake: using transactional memory in an interactive mulitplayer game Server	Zyulkyarov, Ferad; Gajinov, Vladimir; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Harris, Tim; Valero Cortés, Mateo
	2010	BSC contributions in energy-aware resource management for large scale distributed systems	Valero Cortés, Mateo; Torres Viñals, Jordi; Ayguadé Parra, Eduard; Carrera Pérez, David; Guitart Fernández, Jordi; Beltran Querol, Vicenç; Becerra Fontal, Yolanda; Badia Sala, Rosa Maria; Labarta Mancho, Jesús José
	2009	Characterizing the resource-sharing levels of the UltraSparc T2 processor	Cakarevic, Vladimir; Radojkovic, Petar; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo
	set-2009	Code semantic-aware runahead threads	Ramírez García, Tanausu; Pajuelo González, Manuel Alejandro; Santana Jaria, Oliverio J.; Valero Cortés, Mateo
	2010	Comparing last-level cache designs for CMP architectures	Vega, Augusto; Rico Carro, Alejandro; Cabarcas, Felipe; Ramírez Bellido, Alejandro; Valero Cortés, Mateo
	jun-2008	Evolutionary system for prediction and optimization of hardware architecture performance	Castillo, Pedro Angel; Merelo, Juan Julián; Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo; Mora, Antonio; Laredo, Juan Luís; McKee, Sally
	23-abr-2009	Exploiting different levels of parallelism in the biological sequence comparison problem	Sánchez Castaño, Friman; Ramírez Bellido, Alejandro; Valero Cortés, Mateo
	2011	From plasma to beefarm: Design experience of an FPGA-based multicore prototype	Sonmez, N.; Arcas, O.; Sayilar, G.; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Hur, Ibrahim; Singh, S.; Valero Cortés, Mateo
	jun-2011	Hybrid transactional memory with pessimistic concurrency control	Vallejo, Enrique; Sanyal, Sutirtha; Harris, Tim; Vallejo, Fernando; Beivide, Ramón; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo
	1990	Implementation of systolic algorithms using pipelined functional units	Valero García, Miguel; Navarro Guerrero, Juan José; Llaberia Griñó, José M.; Valero Cortés, Mateo
	2011	Integrating dataflow abstractions into transactional memory	Gajinov, Vladimir; Milovanovic, Milos; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo
	jun-2009	Internet traffic and the behavior of processing workloads	Zilan, Ruken; Verdú Mulà, Javier; García Vidal, Jorge; Nemirovsky, Mario; Valero Cortés, Mateo
	2010	ITCA: Inter-Task Conflict-Aware CPU accounting for CMP	Luque, Carlos; Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Valero Cortés, Mateo
	2009	ITCA: inter-task conflict-aware CPU accounting for CMPs	Luque, Carlos; Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Buyuktosunoglu, Alper; Valero Cortés, Mateo
	2010	Long DNA sequence comparison on multicore architectures	Sánchez Castaño, Friman; Cabarcas, Felipe; Ramírez Bellido, Alejandro; Valero Cortés, Mateo