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Llistant per Autor Calomarde Palomino, Antonio

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Mostrant resultats 1 a 12 de 12
Vista preliminarDataTítolAutor(s)
05548578.pdf.jpg2010A comprehensive compensation technique for process variations and environmental fluctuations in digital integrated circuitsAndrade Miceli, Dennis Michael; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio
2011A new probabilistic design methodology of nanoscale digital circuitsGarcía Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio
2013A single event transient hardening circuit design technique based on strengtheningCalomarde Palomino, Antonio; Amat Bertran, Esteve; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio
2011Analysis of delay mismatching of digital circuits caused by common environmental fluctuationsAndrade Miceli, Dennis Michael; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio; Cotofana, Sorin
DCIS2012_JPP.pdf.jpg2012Closed loop controlled ring oscillator: a variation tolerant self-adaptive clock generation architecturePérez Puigdemont, Jordi; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja
20-nov-2013Impact of finfet and III-V/Ge technology on logic and memory cell behaviorAmat, Esteve; Calomarde Palomino, Antonio; García Almudéver, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio
des-2011New redundant logic design concept for high noise and low voltage scenariosGarcía Leyva, Lancelot; Andrade Miceli, Dennis Michael; Gómez Fernández, Sergio; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio
2013Novel redundant logic design for noisy low voltage scenariosGarcía Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio
2013Reliability study on technology trends beyond 20nmAmat Bertran, Esteve; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio
A SET and Noise Fault Tolerant Circuit Design Technique.pdf.jpg1-abr-2014SET and noise fault tolerant circuit design techniques: application to 7 nm FinFETCalomarde Palomino, Antonio; Amat Bertran, Esteve; Moll Echeto, Francisco de Borja; Vigara Campmany, Julio Enrique; Rubio Sola, Jose Antonio
05548845.pdf.jpg2010Turtle Logic: A new probabilistic design methodology of nanoscale digital circuitsGarcía Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio
Turtle logic....pdf.jpg2010Turtle logic: Novel IC digital probabilistic design methodologyGarcía Leyva, Lancelot; Rubio Sola, Jose Antonio; Moll Echeto, Francisco de Borja; Calomarde Palomino, Antonio
Mostrant resultats 1 a 12 de 12

 

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