Exploració per autor "Rodríguez Montañés, Rosa"
Ara es mostren els items 1-20 de 43
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8T SRAM Cell with Open Defects under Voltage and Timing Variations
(2011)
Text en actes de congrés
Accés obert -
A combinatorial method for the evaluation of yield of fault-tolerant systems-on-chip
(2003)
Text en actes de congrés
Accés obertIn this paper we develop a combinatorial method for the evaluation of yield of fault-tolerant systems-on-chip. The method assumes that defects are produced according to a model in which defects are lethal and affect given ... -
Adaptació del mapa actual de competències transversals de l'ETSEIB a l'EEES
(Universitat Politècnica de Catalunya. Institut de Ciències de l'Educació, 2010-02-11)
Comunicació de congrés / Text en actes de congrés
Accés obertUn dels objectius principals del projecte consisteix en la detecció, classificació i anàlisi de les competències transversals/genèriques que s'estan treballant dins les assignatures troncals i/o optatives de l'actual pla ... -
Backside polishing detector: a new protection against backside attacks
(2015)
Text en actes de congrés
Accés obertSecure chips are in permanent risk of attacks. Physical attacks usually start removing part of the package and accessing the dice by different means: laser shots, electrical or electromagnetic probes, etc. Doing this ... -
BIST Architecture to Detect Defects in TSVs During Pre-Bond Testing
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialThrough Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs). The detection of defective TSVs in the earliest process step is of major concern. Hence, testing TSVs is usually done ... -
Caracterització elèctrica de circuits CMOS digitals amb defectes tipus pont: implicacions al test per corrent quiescent
(Universitat Politècnica de Catalunya, 1992-12-17)
Tesi
Accés obertLa tesis contribuye a los esfuerzos dirigidos a la consecución de modelaciones precisas de los fallos de tipo puente. La tecnología de los circuitos digitales considerados es la CMOS estática. En la tesis se utiliza un ... -
CLIL implementation at a Spanish university: A pilot experience
(Universidad de Zaragoza, Prensas Universitarias de Zaragoza, 2011)
Comunicació de congrés
Accés restringit per política de l'editorial -
Crypto-test-lab for security validation of ECC co-processor test infrastructure
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés obertElliptic Curve Cryptography (ECC) is a technology for public-key cryptography that is becoming increasingly popular because it provides greater speed and implementation compactness than other public-key technologies. ... -
Defective Behaviour of an 8T SRAM Cell with Open Defects
(2010)
Text en actes de congrés
Accés restringit per política de l'editorial -
Diagnosis of full open defects in interconnect lines with fan-out
(IEEE Press. Institute of Electrical and Electronics Engineers, 2010-05-24)
Text en actes de congrés
Accés obertThe development of accurate diagnosis methodologies is important to solve process problems and achieve fast yield improvement. As open defects are common in CMOS technologies, accurate diagnosis of open defects becomes ... -
Diagnosis of full open defects in interconnecting lines
(IEEE, 2007-05-31)
Text en actes de congrés
Accés obertA proposal for enhancing the diagnosis of full open defects in interconnecting lines of CMOS circuits is presented. The defective line is first classified as fully opened by means of a logic-based diagnosis tool (Faloc). ... -
Enhanced serial RRAM cell for unpredictable bit generation
(2021-05)
Article
Accés obertIn this letter, the serial configuration of two RRAMs is used as a basic cell to generate an unpredictable bit. The basis of the operation considers starting from the Low Resistive State (LRS) in both devices (initialization ... -
ETS 2022 ORGANIZING COMMITTEE
(2022-05)
Text en actes de congrés
Accés obert -
Gate leakage impact on full open defects in interconnect lines
(2011-06)
Article
Accés obertAn Interconnect full open defect breaks the connection between the driver and the gate terminals of downstream transistors, generating a floating line. The behavior of floating lines is known to depend on several factors, ... -
Impact of gate tunnelling leakage on CMOS circuits with full open defects
(Institution of Electrical Engineers, 2007-10)
Article
Accés obertInterconnecting lines with full open defects become floating lines. In nanometric CMOS technologies, gate tunnelling leakage currents impact the behaviour of these lines, which cannot be considered electrically isolated ... -
Impact of laser attacks on the switching behavior of RRAM devices
(2020-01-20)
Article
Accés obertThe ubiquitous use of critical and private data in electronic format requires reliable and secure embedded systems for IoT devices. In this context, RRAMs (Resistive Random Access Memories) arises as a promising alternative ... -
Integració i avaluació de competències genèriques als Graus de l'ETSEIB
(Universitat Politècnica de Catalunya. Institut de Ciències de l'Educació, 2012-02-07)
Comunicació de congrés / Text en actes de congrés
Accés obert -
Lecturer and student perceptions on CLIL at a spanish university
(Taylor & Francis, 2011)
Article
Accés restringit per política de l'editorialThis study reports on a pilot implementation of Content and Language Integrated Learning (CLIL) at a Spanish university. In order to find out how both lecturers and students perceived their experience, several interviews ... -
Localization and electrical characterization of interconnect open defects
(2010-02)
Article
Accés obertA technique for extracting the electrical and topological parameters of open defects in process monitor lines is presented. The procedure is based on frequency-domain measurements performed at both end points of the ... -
Low Cost AES Protection Against DPA Using Rolling Codes
(Curran Associates, Inc., 2021)
Text en actes de congrés
Accés restringit per política de l'editorialMany block cipher algorithms like AES are known to be weak against differential power analysis attacks (DPA) if the executing unit presents certain levels of information leakage, which is a common problem in microprocessors. ...
