Exploració per autor "Navarro, Nacho"
Ara es mostren els items 1-20 de 35
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A library implementation of the nano-threads programming model
(Springer, 1996)
Text en actes de congrés
Accés obertIn this paper we describe the design and implementation of a user-level thread package based on the nano-threads programming model, whose goal is to efficiently manage the application parallelism at user-level. Nano-thread ... -
Adaptive runtime-assisted block prefetching on chip-multiprocessors
(2016-04-29)
Article
Accés obertMemory stalls are a significant source of performance degradation in modern processors. Data prefetching is a widely adopted and well studied technique used to alleviate this problem. Prefetching can be performed by the ... -
Adjust of solar cell model parameters based in MATLAB
(M. C. Acero, M. Lozano - CNM-CSIC, 2003)
Comunicació de congrés
Accés restringit per política de l'editorialIn this work, a model parameter extractor of solar cells using Matlab is shown. The software, developed in Matlab environment, has been successfully applied to study internal characteristics of photovoltaic devices [1-2], ... -
An asymmetric distributed shared memory model for heterogeneous parallel systems
(2010)
Text en actes de congrés
Accés obertHeterogeneous computing combines general purpose CPUs with accelerators to efficiently execute both sequential control-intensive and data-parallel phases of applications. Existing programming models for heterogeneous ... -
An in-operation planning tool architecture for flexgrid network re-optimization
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialIn-operation network planning consists in re-optimizing a network, currently being operated to transport traffic, either minimizing resource utilization or maximizing the transported traffic. In the context of flexgrid ... -
An open benchmark implementation for multi-CPU multi-GPU pedestrian detection in automotive systems
(IEEE, 2017-12-14)
Comunicació de congrés
Accés obertModern and future automotive systems incorporate several Advanced Driving Assistance Systems (ADAS). Those systems require significant performance that cannot be provided with traditional automotive processors and programming ... -
Analyzing performance improvements and energy savings in Infiniband architecture using network compression
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialOne of the greatest challenges in HPC is total system power and energy consumption. Whereas HPC interconnects have traditionally been designed with a focus on bandwidth and latency, there is an increasing interest in ... -
Applying interposition techniques for performance analysis of OPENMP parallel applications
(Institute of Electrical and Electronics Engineers (IEEE), 2000)
Text en actes de congrés
Accés obertTuning parallel applications requires the use of effective tools for detecting performance bottlenecks. Along a parallel program execution, many individual situations of performance degradation may arise. We believe that ... -
Architecture of a specialized back-end high performance computing-based PCE for flexgrid networks
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialThe requirement of executing network re-optimization operations to efficiently manage and deploy new generation flexgrid-based optical networks has brought to light the need of some specialized PCEs capable of performing ... -
CODOMs: Protecting software with code-centric memory domains
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialToday's complex software systems are neither secure nor reliable. The rudimentary software protection primitives provided by current hardware forces systems to run many distrusting software components (e.g., procedures, ... -
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures
(Association for Computing Machinery (ACM), 2015)
Text en actes de congrés
Accés obertThe increasing number of cores in manycore architectures causes important power and scalability problems in the memory subsystem. One solution is to introduce scratchpad memories alongside the cache hierarchy, forming a ... -
Comparison based sorting for systems with multiple GPUs
(Association for Computing Machinery (ACM), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialAs a basic building block of many applications, sorting algorithms that efficiently run on modern machines are key for the performance of these applications. With the recent shift to using GPUs for general purpose compuing, ... -
CUsched: multiprogrammed workload scheduling on GPU architectures
(2013)
Report de recerca
Accés obertGraphic Processing Units (GPUs) are currently widely used in High Performance Computing (HPC) applications to speed-up the execution of massively-parallel codes. GPUs are well-suited for such HPC environments because ... -
Data stream classification using random feature functions and novel method combinations
(2017-05-01)
Article
Accés obertBig Data streams are being generated in a faster, bigger, and more commonplace. In this scenario, Hoeffding Trees are an established method for classification. Several extensions exist, including high performing ensemble ... -
Design space explorations for streaming accelerators using streaming architectural simulator
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés obertIn the recent years streaming accelerators like GPUs have been pop-up as an effective step towards parallel computing. The wish-list for these devices span from having a support for thousands of small cores to a nature ... -
Direct Inter-Process Communication (dIPC): Repurposing the CODOMs architecture to accelerate IPC
(Association for Computing Machinery (ACM), 2017)
Text en actes de congrés
Accés obertIn current architectures, page tables are the fundamental mechanism that allows contemporary OSs to isolate user processes, binding each thread to a specific page table. A thread cannot therefore directly call another ... -
Efficient exception handling support for GPUs
(Association for Computing Machinery (ACM), 2017)
Text en actes de congrés
Accés restringit per política de l'editorialOperating systems have long relied on the exception handling mechanism to implement numerous virtual memory features and optimizations. However, today's GPUs have a limited support for exceptions, which prevents implementation ... -
Enabling preemptive multiprogramming on GPUs
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés obertGPUs are being increasingly adopted as compute accelerators in many domains, spanning environments from mobile systems to cloud computing. These systems are usually running multiple applications, from one or several users. ... -
Experimental assessment of a high performance back-end PCE for Flexgrid optical network re-optimization
(The Optical Society (OSA), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialA specialized high performance Graphics Processing Unit (GPU)-based back-end Path Computation Element (PCE) to compute re-optimization in Flexgrid networks is presented. Experimental results show 6x speedups compared to ... -
Hardware-software coherence protocol for the coexistence of caches and local memories
(2015-01-01)
Article
Accés obertCache coherence protocols limit the scalability of multicore and manycore architectures and are responsible for an important amount of the power consumed in the chip. A good way to alleviate these problems is to introduce ...
