Ara es mostren els items 1-11 de 11

  • DIA: A complexity-effective decoding architecture 

    Santana Jaria, Oliverio J.; Falcón Samper, Ayose Jesus; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2009-04)
    Article
    Accés obert
    Fast instruction decoding is a true challenge for the design of CISC microprocessors implementing variable-length instructions. A well-known solution to overcome this problem is caching decoded instructions in a hardware ...
  • Enlarging instruction streams 

    Santana Jaria, Oliverio J.; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2007-10)
    Article
    Accés obert
    The stream fetch engine is a high-performance fetch architecture based on the concept of an instruction stream. We call a sequence of instructions from the target of a taken branch to the next taken branch, potentially ...
  • Introducing runahead threads 

    Ramírez García, Tanausu; Pajuelo González, Manuel Alejandro; Santana Jaria, Oliverio J.; Valero Cortés, Mateo (2007-07)
    Report de recerca
    Accés obert
    Simultaneous Multithreading processors share their resources among multiple threads in order to improve performance. However, a resource control policy is needed to avoid resource conflicts and prevent some threads from ...
  • Kilo-instruction processors: overcoming the memory wall 

    Cristal Kestelman, Adrián; Santana Jaria, Oliverio J.; Cazorla, Francisco; Galluzzi, Marco; Ramirez Garcia, Tanausú; Pericas, Miquel; Valero Cortés, Mateo (2005-05)
    Article
    Accés obert
    Historically, advances in integrated circuit technology have driven improvements in processor microarchitecture and led to todays microprocessors with sophisticated pipelines operating at very high clock frequencies. ...
  • Latency tolerant branch predictors 

    Santana Jaria, Oliverio J.; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (IEEE Press, 2003)
    Text en actes de congrés
    Accés obert
    The access latency of branch predictors is a well known problem of fetch engine design. Prediction overriding techniques are commonly accepted to overcome this problem. However, prediction overriding requires a complex ...
  • Maximizing multithreaded multicore architectures through thread migrations 

    Acosta Ojeda, Carmelo Alexis; Cazorla Almeida, Francisco Javier; Santana Jaria, Oliverio J.; Falcón Samper, Ayose Jesús; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2009)
    Report de recerca
    Accés obert
    Heterogeneity in general-purpose workloads often end up in non optimal per-thread hardware resource usage. The current trend towards multicore architectures, containing several multithreaded cores, increases the need of a ...
  • On the problem of evaluating the performance of multiprogrammed workloads 

    Cazorla, Francisco; Pajuelo González, Manuel Alejandro; Santana Jaria, Oliverio J.; Fernández Rodríguez, José Enrique; Valero Cortés, Mateo (2010-12)
    Article
    Accés obert
    Multithreaded architectures are becoming more and more popular. In order to evaluate their behavior, several methodologies and metrics have been proposed. A methodology defines when the measurements for a given workload ...
  • Predicting multiple streams per cycle 

    Santana Jaria, Oliverio J.; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2005)
    Report de recerca
    Accés obert
    The next stream predictor is an accurate branch predictor that provides stream level sequencing. Every stream prediction contains a full stream of instructions, that is, a sequence of instructions from the target of a taken ...
  • ROB-free architecture proposal 

    González, Isidro; Galluzzi, Marco; Cristal Kestelman, Adrián; Pajuelo González, Manuel Alejandro; Santana Jaria, Oliverio J.; Valero Cortés, Mateo (2007-09)
    Report de recerca
    Accés obert
    Modern processors improve performance by taking advantage of the instruction level parallelism (ILP) by means of allowing hundreds of instructions in flight. However, they still have to face an important source of degradation ...
  • Runahead threads to improve SMT performance 

    Ramirez Garcia, Tanausú; Pajuelo González, Manuel Alejandro; Santana Jaria, Oliverio J.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
    Text en actes de congrés
    Accés obert
    In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded (SMT) processors. Our technique converts ...
  • Techniques for enlarging instruction streams 

    Santana Jaria, Oliverio J.; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2005-03)
    Report de recerca
    Accés obert
    This work presents several techniques for enlarging instruction streams. We call stream to a sequence of instructions from the target of a taken branch to the next taken branch, potentially containing multiple basic blocks. ...