• Lithography aware regular cell design based on a predictive technology model 

      Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja (2010-12)
      Article
      Accés restringit per política de l'editorial
      As semiconductor technology advances into the nanoscale era, optical effects such as channel narrowing, corner rounding or line-end pullback are critical to accomplish circuit yield specifications. It is well-demonstrated ...
    • Via-configurable transistors array: a regular design technique to improve ICs yield 

      Pons, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2007)
      Text en actes de congrés
      Accés obert
      Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That is why regular techniques with different degrees of regularity are emerging as possible solutions. Our ...