Exploració per tema "Computer storage devices -- Design and construction"

Ara es mostren els items 1-4 de 4

    • A Dynamically Adaptable Hardware Transactional Memory 

      Lupon Navazo, Marc; Magklis, Grigorios; González Colás, Antonio María (IEEE Computer Society Publications, 2010)
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      Most Hardware Transactional Memory (HTM) implementations choose fixed version and conflict management policies at design time. While eager HTM systems store transactional state in-place in memory and resolve conflicts ...

    • Hybrid transactional memory with pessimistic concurrency control 

      Vallejo, Enrique; Sanyal, Sutirtha; Harris, Tim; Vallejo, Fernando; Beivide, Ramón; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2011-06)
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      Transactional Memory (TM) intends to simplify the design and implementation of the shared-memory data structures used in parallel software. Many Software TM systems are based on writer-locks to protect the data being ...

    • Interleaving granularity on high bandwidth memory architecture for CMPs 

      Cabarcas, Felipe; Rico Carro, Alejandro; Etsion, Yoav; Ramírez Bellido, Alejandro (IEEE Computer Society Publications, 2010)
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      Memory bandwidth has always been a critical factor for the performance of many data intensive applications. The increasing processor performance, and the advert of single chip multiprocessors have increased the memory ...

    • MFLUSH: handling long-latency loads in SMT on-chip multiprocessors 

      Acosta Ojeda, Carmelo Alexis; Cazorla Almeida, Francisco Javier; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (IEEE Computer Society Publications, 2008)
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      Nowadays, there is a clear trend in industry towards employing the growing amount of transistors on chip in replicating execution cores (CMP), where each core is Simultaneous Multithreading (SMT). State-of-the-art ...