Exploració per tema "Clock gating"
Ara es mostren els items 1-2 de 2
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A retargetable and accurate methodology for logic-IP-internal electromigration assessment
(2015)
Text en actes de congrés
Accés obertA new methodology for SoC-level logic-IP-internal EM verification is presented, which provides an on-the-fly retargeting capability for reliability constraints. This flexibility is available at the design verification ... -
Clock gate on abort: Towards energy-efficient hardware transactional memory
(Institute of Electrical and Electronics Engineers (IEEE), 2009)
Text en actes de congrés
Accés obertTransactional Memory (TM) is an emerging technology which promises to make parallel programming easier compared to earlier lock based approaches. However, as with any form of speculation, Transactional Memory too wastes a ...
