Exploració per tema "Circuits lògics"
Ara es mostren els items 1-20 de 42
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A fast and retargetable framework for logic-IP-internal electromigration assessment comprehending advanced waveform effects
(2016-06-01)
Article
Accés obertA new methodology for system-on-chip-level logic-IP-internal electromigration verification is presented in this paper, which significantly improves accuracy by comprehending the impact of the parasitic RC loading and ... -
A general model for performance optimization of sequential systems
(Institute of Electrical and Electronics Engineers (IEEE), 2007)
Text en actes de congrés
Accés obertRetiming, c-slow retiming and recycling are different transformations for the performance optimization of sequential circuits. For retiming and c-slow retiming, different models that provide exact solutions have already ... -
A hierarchical mathematical model for automatic pipelining and allocation using elastic systems
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés obertThe advent of FPGA-based accelerators has encouraged the use of high-level synthesis (HLS) for rapid prototyping and design space exploration. In this context, design optimization at behavioral level becomes a critical ... -
A low-power RF front-end for 2.5 GHz receivers
(Institute of Electrical and Electronics Engineers (IEEE), 2008)
Text en actes de congrés
Accés obertThis paper presents a low power and low cost front end for a direct conversion 2.5 GHz ISM band receiver composed of a 16 kV HBM ESD protected LNA, differential Gilbert-cell mixers, and high-pass filters for DC offset ... -
A multi-radix approach to asynchronous division
(Institute of Electrical and Electronics Engineers (IEEE), 2001)
Text en actes de congrés
Accés obertThe speed of high-radix digit-recurrence dividers is mainly determined by the hardware complexity of the quotient-digit selection function. In this paper we present a scheme that combines the area efficiency of bundled ... -
A new look at the conditions for the synthesis of speed-independent circuits
(Institute of Electrical and Electronics Engineers (IEEE), 1995)
Text en actes de congrés
Accés obertThis paper presents a set of sufficient conditions for the gate-level synthesis of speed-independent circuits when constrained to a given class of gate library. Existing synthesis methodologies are restricted to architectures ... -
A radix-16 SRT division unit with speculation of the quotient digits
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Text en actes de congrés
Accés obertThe speed of a divider based on a digit-recurrence algorithm depends mainly on the latency of the quotient digit generation function. In this paper we present an analytical approach that extends the theory developed for ... -
A single event transient hardening circuit design technique based on strengthening
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialIn a near future of high-density and low-power technologies, the study of soft errors will not only be relevant for memory systems and latches of logic circuits, but also for the combinational parts of logic circuits which ... -
An experimental approach to Memristive Devices and its applications on Stateful Logic : Design and experimental evaluation of the IMPLY logic gate with Knowm memristors
(Universitat Politècnica de Catalunya, 2017-06-15)
Treball Final de Grau
Accés obertRecent discovery (2008) of the non-volatile binary resistances known as memristors has attracted new scientific research opportunities. These include novel approaches to present-day technology such as memory storage, ... -
Conception d'un filtre Analogique / Numérique
(Universitat Politècnica de Catalunya, 2013-09-10)
Projecte Final de Màster Oficial
Accés obert[ANGLÈS] In this thesis, a tunable analog filter with digital control is presented. The digital control is implemented by means of a Spartan 3A FPGA and programmable resistors. The system consists of two identical tunable ... -
Coping with the variability of combinational logic delays
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Text en actes de congrés
Accés obertThis paper proposes a technique for creating a combinational logic network with an output that signals when all other outputs have stabilized. The method is based on dual-rail encoding, and guarantees low timing overhead ... -
Correct-by-construction microarchitectural pipelining
(Institute of Electrical and Electronics Engineers (IEEE), 2008)
Text en actes de congrés
Accés obertThis paper presents a method for correct-by-construction microarchitectural pipelining that handles cyclic systems with dependencies between iterations. Our method combines previously known bypass and retiming transformations ... -
Decomposition and technology mapping of speed-independent circuits using Boolean relations
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Text en actes de congrés
Accés obertPresents a new technique for the decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available in ... -
Decomposition and technology mapping of speed-independent circuits using Boolean relations
(1999-09)
Article
Accés obertThis paper presents a new technique for decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available ... -
Design and implementation of a 5/spl times/5 trits multiplier in a quasi-adiabatic ternary CMOS logic
(1998-07)
Article
Accés obertAdiabatic switching is a technique to design low-power digital IC's. Fully adiabatic logics have expensive silicon area requirements. To solve this drawback, a quasi-adiabatic ternary logic is proposed. Its basis is ... -
Designing asynchronous circuits from behavioural specifications with internal conflicts
(Institute of Electrical and Electronics Engineers (IEEE), 1994)
Text en actes de congrés
Accés obertThe paper presents a systematic method for synthesizing asynchronous circuits from event-based specifications with conflicts on output signals. It describes a set of semantic-preserving transformations performed at the ... -
Division with speculation of quotient digits
(Institute of Electrical and Electronics Engineers (IEEE), 1993)
Text en actes de congrés
Accés obertThe speed of SRT-type dividers is mainly determined by the complexity of the quotient-digit selection, so that implementations are limited to low-radix stages. A scheme is presented in which the quotient-digit is speculated ... -
Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies
(2020-03)
Article
Accés obertMoore’s Law predicted that the number of transistors on a chip would double approximately every 2 years. However, this trend is arriving at an impasse. Optimizing the usage of the available transistors within the thermal ... -
Evaluating A+B=K conditions in constant time
(Institute of Electrical and Electronics Engineers (IEEE), 1988)
Text en actes de congrés
Accés obertThe authors consider a type of condition that can be evaluated without requiring a complete ALU (arithmetic logic unit) operation. The circuit that is presented detects the condition A+B=K (n-bit numbers) in constant time, ... -
Evaluation of A+B=K conditions without carry propagation
(Institute of Electrical and Electronics Engineers (IEEE), 1992-11)
Article
Accés obertThe response time of parallel adders is mainly determined by the carry propagation delay. The evaluation of conditions of the type A+B=K is addressed. Although an addition is involved in the comparison, it is shown that ...
