Exploració per tema "Chip multi-processors (CMPs)"

Ara es mostren els items 1-3 de 3

    • Data conversion in area-constrained applications: the wireless network-on-chip case 

      Abadal Cavallé, Sergi; Alarcón Cot, Eduardo José (Institute of Electrical and Electronics Engineers (IEEE), 2018)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Network-on-Chip (NoC) is currently the paradigm of choice to interconnect the different components of System-on-Chips (SoCs) or Chip Multiprocessors (CMPs). As the levels of integration continue to grow, however, current ...

    • Framework for economical error recovery in embedded cores 

      Upasani, Gaurang; Vera Rivera, Francisco Javier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2014)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      The vulnerability of the current and future processors towards transient errors caused by particle strikes is expected to increase rapidly because of exponential growth rate of on-chip transistors, the lower voltages and ...

    • TaskGenX: A Hardware-Software Proposal for Accelerating Task Parallelism 

      Chronaki, Kallia; Casas, Marc; Moretó Planas, Miquel; Bosch Pons, Jaume; Badia Sala, Rosa Maria (Springer, 2018-05-29)
      Comunicació de congrés
      Accés obert
      As chip multi-processors (CMPs) are becoming more and more complex, software solutions such as parallel programming models are attracting a lot of attention. Task-based parallel programming models offer an appealing approach ...