Exploració per tema "Cache memory -- Security measures"

Ara es mostren els items 1-3 de 3

    • A security model for randomization-based protected caches 

      Ribes González, Jordi; Farràs Ventura, Oriol; Hernández Luz, Carles; Kostalabros, Vatistas; Moretó Planas, Miquel (2022)
      Article
      Accés obert
      Cache side-channel attacks allow adversaries to learn sensitive information about co-running processes by using only access latency measures and cache contention. This vulnerability has been shown to lead to several ...

    • Defeating simple power analysis attacks in cache memories 

      Neagu, Madalin; Manich Bou, Salvador; Miclea, Liviu (Institute of Electrical and Electronics Engineers (IEEE), 2015)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      A wide range of attacks that target cache memories in secure systems have been reported in the last half decade. Cold-boot attacks can be thwarted through the recently proposed Interleaved Scrambling Technique (IST). ...

    • Improving security in cache memory by power efficient scrambling technique 

      Neagu, Madalin; Miclea, Liviu; Manich Bou, Salvador (2015-04-08)
      Article
      Accés restringit per política de l'editorial
      The last decade has recorded an increase in security protocols for integrated circuits and memory systems, because of device specific attacks such as side-channel monitoring and cold boot and also because sensitive information ...