Exploració per tema "Cache"

Ara es mostren els items 1-7 de 7

    • APPLE: Adaptive performance-predictable low-energy caches for reliable hybrid voltage operation 

      Maric, Bojan; Abella Ferrer, Jaume; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2013)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Semiconductor technology evolution enables the design of resource-constrained battery-powered ultra-low-cost chips required for new market segments such as environment, urban life and body monitoring. Caches have been shown ...

    • Cache side-channel attacks and time-predictability in high-performance critical real-time systems 

      Trilla Rodríguez, David; Hernández Luz, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2018-06-24)
      Comunicació de congrés
      Accés obert
      Embedded computers control an increasing number of systems directly interacting with humans, while also manage more and more personal or sensitive information. As a result, both safety and security are becoming ubiquitous ...

    • Contention tracking in GPU last-level cache 

      Barrera Herrera, Javier Enrique; Kosmidis, Leonidas; Tabani, Hamid; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2022)
      Text en actes de congrés
      Accés obert
      The Last-level cache (LLC) is one of the main GPU’s shared resources that contributes to improve performance but also increases individual kernel’s performance variability. This is detrimental in scenarios in which some ...

    • DTM-NUCA: dynamic texture mapping-NUCA for energy-efficient graphics rendering 

      Corbalán Navarro, David; Aragón, Juan Luis; Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2022)
      Text en actes de congrés
      Accés obert
      Modern mobile GPUs integrate an increasing number of shader cores to speedup the execution of graphics workloads. Each core integrates a private Texture Cache to apply texturing effects on objects, which is backed-up by a ...

    • Lightweight register file caching in collector units for GPUs 

      Abaie Shoushtary, Mojtaba; Arnau Montañés, José María; Tubella Murgadas, Jordi; González Colás, Antonio María (Association for Computing Machinery (ACM), 2023)
      Text en actes de congrés
      Accés obert
      Modern GPUs benefit from a sizable Register File (RF) to provide fine-grained thread switching. As the RF is huge and accessed frequently, it consumes a considerable share of the dynamic energy of the GPU. Designing a ...

    • Measurement-based cache representativeness on multipath programs 

      Milutinovic, Suzana; Abella Ferrer, Jaume; Mezzetti, Enrico; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2018-06)
      Comunicació de congrés
      Accés obert
      Autonomous vehicles in embedded real-time systems increase critical-software size and complexity whose performance needs are covered with high-performance hardware features like caches, which however hampers obtaining WCET ...

    • Task scheduling sensitivity to L1 cache settings on an area-constrained 32-core RISC-V processor 

      Morais, Lucas; Jiménez-González, Daniel; Álvarez, Carlos (Barcelona Supercomputing Center, 2022-05)
      Text en actes de congrés
      Accés obert
      High-performance applications are highly sensitive to memory performance characteristics. While programs with comparatively low memory-to-computation ratio are less likely to be hampered by limited memory bandwidth, most ...