Exploració per autor "Arcas Abella, Oriol"

Ara es mostren els items 1-7 de 7

    • An empirical evaluation of High-Level Synthesis languages and tools for database acceleration 

      Arcas Abella, Oriol; Ndu, Geoffrey; Sönmez, Nehir; Ghasempour, Mohsen; Armejach, Adrià; Navaridas, Javier; Song, Wei; Mawer, John; Cristal Kestelman, Adrián; Lujan, Mikel (Institute of Electrical and Electronics Engineers (IEEE), 2014)
      Text en actes de congrés
      Accés obert
      High Level Synthesis (HLS) languages and tools are emerging as the most promising technique to make FPGAs more accessible to software developers. Nevertheless, picking the most suitable HLS for a certain class of algorithms ...

    • Beehive: an FPGA-based multiprocessor architecture 

      Arcas Abella, Oriol (Universitat Politècnica de Catalunya, 2009-09-23)
      Projecte Final de Màster Oficial
      Accés obert
      In recent years, to accomplish with the Moore's law hardware and software designers are tending progressively to focus their efforts on exploiting instruction-level parallelism. Software simulation has been essential for ...

    • From plasma to beefarm: Design experience of an FPGA-based multicore prototype 

      Sonmez, Nehir; Arcas Abella, Oriol; Sayilar, Gokhan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Hur, Ibrahim; Singh, Satnam; Valero Cortés, Mateo (Springer, 2011)
      Text en actes de congrés
      Accés obert
      In this paper, we take a MIPS-based open-source uniprocessor soft core, Plasma, and extend it to obtain the Beefarm infrastructure for FPGA-based multiprocessor emulation, a popular research topic of the last few years ...

    • Hardware acceleration for query processing: Leveraging FPGAs, CPUs, and memory 

      Arcas Abella, Oriol; Armejach Sanosa, Adrià; Hayes, Timothy; Malazgirt, Görker Alp; Palomar Pérez, Óscar; Salami, Behzad; Sonmez, Nehir (2016-01)
      Article
      Accés obert
      Database management systems have become an indispensable tool for industry, government, and academia, and form a significant component of modern datacenters. They can be used in a multitude of scenarios, including online ...

    • Improving TCP performance and reducing self-induced congestion with receive window modulation 

      Ciaccia, Francesco; Arcas Abella, Oriol; Montero Banegas, Diego Teodoro; Romero Ruiz, Ivan; Milito, Rodolfo; Serral Gracià, René; Nemirovsky, Mario (2019)
      Text en actes de congrés
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      We present a control module for software edge routers called Receive Window Modulation - RWM. Its main objective is to mitigate what we define as self-induced congestion: the result of traffic emission patterns at the ...

    • Multicore architecture prototyping on reconfigurable devices 

      Arcas Abella, Oriol (Universitat Politècnica de Catalunya, 2016-04-15)
      Tesi
      Accés obert
      In the the last decades several performance walls were hit. The memory wall and the power wall are limiting the performance scaling of digital microprocessors. Homogeneous multicores rely on thread-level parallelism, which ...

    • SABES: Statistical Available Bandwidth EStimation from passive TCP measurements 

      Ciaccia, Francesco; Romero Ruiz, Ivan; Arcas Abella, Oriol; Montero Banegas, Diego Teodoro; Serral Gracià, René; Nemirovsky, Mario (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Text en actes de congrés
      Accés obert
      Estimating available network resources is fundamental when adapting the sending rate both at the application and transport layer. Traditional approaches either rely on active probing techniques or iteratively adapting the ...