• El Debate como instrumento docente para trabajar las competencias transversales y la ética en la profesión informática 

    Vallejo, Fernando; Zorrilla, Marta (Universidad de Almería, 2016-07-05)
    Comunicació de congrés
    Accés obert
    Entre las competencias que todos los egresados de los grados en Ingeniería Informática deben tener se encuentra la ética en el ejercicio de la profesión informática. En este trabajo se presenta una experiencia docente ...
  • Hybrid transactional memory with pessimistic concurrency control 

    Vallejo, Enrique; Sanyal, Sutirtha; Harris, Tim; Vallejo, Fernando; Beivide, Ramón; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2011-06)
    Article
    Accés restringit per política de l'editorial
    Transactional Memory (TM) intends to simplify the design and implementation of the shared-memory data structures used in parallel software. Many Software TM systems are based on writer-locks to protect the data being ...
  • Implementing kilo-instruction multiprocessors 

    Vallejo, Enrique; Galluzzi, Marco; Cristal Kestelman, Adrián; Vallejo, Fernando; Beivide Palacio, Ramon; Stenström, Per; Smith, James E.; Valero Cortés, Mateo (2005)
    Report de recerca
    Accés obert
    Multiprocessors are coming into wide-spread use in many application areas, yet there are a number of challenges to achieving a good tradeoff between complexity and performance. For example, while implementing memory coherence ...
  • Implicit transactional memory in chip multiprocessors 

    Galluzzi, Marco; Vallejo, Enrique; Cristal Kestelman, Adrián; Vallejo, Fernando; Beivide Palacio, Ramon; Stenström, Per; Smith, James E.; Valero Cortés, Mateo (2007-06)
    Report de recerca
    Accés obert
    Chip Multiprocessors (CMPs) are an efficient way of designing and use the huge amount of transistors on a chip. Different cores on a chip can compose a shared memory system with a very low-latency interconnect at a very ...
  • Implicit transactional memory in kilo-instruction multiprocessors 

    Galluzzi, Marco; Vallejo, Enrique; Cristal Kestelman, Adrián; Vallejo, Fernando; Beivide Palacio, Julio Ramon; Stenström, Per; Smith, James E.; Valero Cortés, Mateo (2007-06)
    Report de recerca
    Accés obert
    Although they have been the main server technology for many years, multiprocessors are undergoing a renaissance due to multi-core chips and the attractive scalability properties of combining a number of such multi-core ...
  • Light NUCA: a proposal for bridging the inter-cache latency gap 

    Suárez, Dario; Monreal Arnal, Teresa; Vallejo, Fernando; Beivide Palacio, Julio Ramón; Viñals Yufera, Víctor (IEEE Computer Society, 2009)
    Comunicació de congrés
    Accés obert
    To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between them and fast L1 caches (inter-cache latency gap). ...
  • Solving multiprocessor drawbacks with kilo-instruction processors 

    Vallejo, Enrique; Galluzzi, Marco; Cristal Kestelman, Adrián; Vallejo, Fernando; Beivide Palacio, Ramon; Stenström, Per; Smith, James E.; Valero Cortés, Mateo (2005)
    Report de recerca
    Accés obert
    Nowadays, a good multiprocessor system design has to deal with many drawbacks in order to achieve a good tradeoff between complexity and performance. For example, while solving problems like coherence and consistency is ...
  • Towards fair, scalable, locking 

    Vallejo, Enrique; Sanyal, Sutirtha; Harris, Tim; Vallejo, Fernando; Beivide Palacio, Ramon; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2008)
    Text en actes de congrés
    Accés obert
    Without care, Hardware Transactional Memory presents several performance pathologies that can degrade its performance. Among them, writers of commonly read variables can suffer from starvation. Though different solutions ...