Ara es mostren els items 1-19 de 19

  • CATA: Criticality aware task acceleration for multicore processors 

    Castillo, Emilio; Moreto Planas, Miquel; Casas, Marc; Álvarez Martí, Lluc; Vallejo, Enrique; Chronaki, Kallia; Badia Sala, Rosa Maria; Bosque Orero, José Luis; Beivide Palacio, Julio Ramón; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    Managing criticality in task-based programming models opens a wide range of performance and power optimization opportunities in future manycore systems. Criticality aware task schedulers can benefit from these opportunities ...
  • Contention-based nonminimal adaptive routing in high-radix networks 

    Fuentes Sáez, Pablo; Vallejo, Enrique; García, Marina; Beivide Palacio, Julio Ramón; Rodríguez, Germán; Minkenberg, Cyriel; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2015)
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    Adaptive routing is an efficient congestion avoidance mechanism for modern Datacenter and HPC networks. Congestion detection traditionally relies on the occupancy of the router queues. However, this approach can hinder ...
  • Efficient routing mechanisms for Dragonfly networks 

    García, Marina; Vallejo, Enrique; Beivide Palacio, Julio Ramón; Odriozola, Miguel; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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    High-radix hierarchical networks are cost-effective topologies for large scale computers. In such networks, routers are organized in super nodes, with local and global interconnections. These networks, known as Dragonflies, ...
  • FlexVC: Flexible virtual channel management in low-diameter networks 

    Fuentes, Pablo; Vallejo, Enrique; Beivide Palacio, Ramon; Minkenberg, Cyriel; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2017)
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    Deadlock avoidance mechanisms for lossless lowdistance networks typically increase the order of virtual channel (VC) index with each hop. This restricts the number of buffer resources depending on the routing mechanism and ...
  • Global misrouting policies in two-level hierarchical networks 

    Garcia, Marina; Vallejo, Enrique; Beivide Palacio, Julio Ramón; Odriozola, Miguel; Camarero Coterillo, Cristobal; Valero Cortés, Mateo; Labarta Mancho, Jesús José; Rodríguez, Germán (2013)
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    Dragonfly networks are composed of interconnected groups of routers. Adaptive routing allows packets to be forwarded minimally or non-minimally adapting to the traffic conditions in the network. While minimal routing sends ...
  • Hybrid transactional memory to accelerate safe lock-based transactions 

    Vallejo, Enrique; Harris, Tim; Cristal Kestelman, Adrián; Unsal, Osman Sabri; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2008)
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    To reduce the overhead of Software Transactional Memory (STM) there are many recent proposals to build hybrid systems that use architectural support either to accelerate parts of a particular STM algorithm (Ha-TM), or ...
  • Hybrid transactional memory with pessimistic concurrency control 

    Vallejo, Enrique; Sanyal, Sutirtha; Harris, Tim; Vallejo, Fernando; Beivide, Ramón; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2011-06)
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    Transactional Memory (TM) intends to simplify the design and implementation of the shared-memory data structures used in parallel software. Many Software TM systems are based on writer-locks to protect the data being ...
  • Implementing kilo-instruction multiprocessors 

    Vallejo, Enrique; Galluzzi, Marco; Cristal Kestelman, Adrián; Vallejo, Fernando; Beivide Palacio, Ramon; Stenström, Per; Smith, James E.; Valero Cortés, Mateo (2005)
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    Multiprocessors are coming into wide-spread use in many application areas, yet there are a number of challenges to achieving a good tradeoff between complexity and performance. For example, while implementing memory coherence ...
  • Implicit transactional memory in chip multiprocessors 

    Galluzzi, Marco; Vallejo, Enrique; Cristal Kestelman, Adrián; Vallejo, Fernando; Beivide Palacio, Ramon; Stenström, Per; Smith, James E.; Valero Cortés, Mateo (2007-06)
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    Chip Multiprocessors (CMPs) are an efficient way of designing and use the huge amount of transistors on a chip. Different cores on a chip can compose a shared memory system with a very low-latency interconnect at a very ...
  • Implicit transactional memory in kilo-instruction multiprocessors 

    Galluzzi, Marco; Vallejo, Enrique; Cristal Kestelman, Adrián; Vallejo, Fernando; Beivide Palacio, Julio Ramon; Stenström, Per; Smith, James E.; Valero Cortés, Mateo (2007-06)
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    Although they have been the main server technology for many years, multiprocessors are undergoing a renaissance due to multi-core chips and the attractive scalability properties of combining a number of such multi-core ...
  • Network unfairness in dragonfly topologies 

    Fuentes, Pablo; Vallejo, Enrique; Camarero, Cristóbal; Beivide Palacio, Ramon; Valero Cortés, Mateo (2016-12)
    Article
    Accés restringit per política de l'editorial
    Dragonfly networks arrange network routers in a two-level hierarchy, providing a competitive cost-performance solution for large systems. Non-minimal adaptive routing (adaptive misrouting) is employed to fully exploit the ...
  • OFAR-CM: Efficient Dragonfly networks with simple congestion management 

    García, Marina; Vallejo, Enrique; Beivide Palacio, Ramon; Valero Cortés, Mateo; Rodríguez, Germán (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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    Dragonfly networks are appealing topologies for large-scale Data center and HPC networks, that provide high throughput with low diameter and moderate cost. However, they are prone to congestion under certain frequent traffic ...
  • On-the-fly adaptive routing for dragonfly interconnection networks 

    García, Marina; Vallejo, Enrique; Beivide Palacio, Julio Ramón; Camarero Coterillo, Cristobal; Valero Cortés, Mateo; Rodríguez Herrera, Germán; Minkenberg, Cyriel (2015-03-01)
    Article
    Accés restringit per política de l'editorial
    Adaptive deadlock-free routing mechanisms are required to handle variable traffic patterns in dragonfly networks. However, distance-based deadlock avoidance mechanisms typically employed in Dragonflies increase the router ...
  • Solving multiprocessor drawbacks with kilo-instruction processors 

    Vallejo, Enrique; Galluzzi, Marco; Cristal Kestelman, Adrián; Vallejo, Fernando; Beivide Palacio, Ramon; Stenström, Per; Smith, James E.; Valero Cortés, Mateo (2005)
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    Nowadays, a good multiprocessor system design has to deal with many drawbacks in order to achieve a good tradeoff between complexity and performance. For example, while solving problems like coherence and consistency is ...
  • Task mapping in rectangular twisted tori 

    Camarero Coterillo, Cristobal; Vallejo, Enrique; Martínez Fernández, Maria del Carmen; Moreto Planas, Miquel; Beivide Palacio, Julio Ramón (Association for Computing Machinery (ACM), 2013)
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    Twisted torus topologies have been proposed as an alternative to toroidal rectangular networks, improving distance parameters and providing network symmetry. However, twisting is apparently less amenable to task mapping ...
  • The Mont-Blanc prototype: an alternative approach for high-performance computing systems 

    Rajovic, Nikola; Ramírez Bellido, Alejandro; Rico, Alejandro; Mantovani, Filippo; Ruiz, Daniel; Villarubi, Oriol; Gómez, Constantino; Backes, Luna; Nieto, Diego; Servat, Harald; Martorell Bofill, Xavier; Labarta Mancho, Jesús José; Ayguadé Parra, Eduard; Valero Cortés, Mateo; Adeniyi-Jones, Chris; Derradji, Said; Gloaguen, Hervé; Lanucara, Piero; Sanna, Nico; Mehaut, Jean-François; Pouget, Kevin; Videau, Brice; Boyer, Eric; Allalen, Momme; Auweter, Axel; Brayford, David; Tafani, Daniele; Brömmel, Dirk; Halver, René; Meinke, Jan H.; Beivide Palacio, Ramon; Benito, Mariano; Vallejo, Enrique (2016)
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    High-performance computing (HPC) is recognized as one of the pillars for further advance of science, industry, medicine, and education. Current HPC systems are being developed to overcome emerging challenges in order to ...
  • The Mont-Blanc prototype: an alternative approach for HPC systems 

    Rajovic, Nikola; Rico, Alejandro; Mantovani, Filippo; Ruiz, Daniel; Vlarrubi, Josep O.; Gomez, Constantino; Backes, Luna; Nieto, Diego; Servat, Harald; Martorell Bofill, Xavier; Labarta Mancho, Jesús José; Ayguadé Parra, Eduard; Adeniyi-Jones, Chris; Derradji, Said; Gloaguen, Hervé; Lanucara, Piero; Sanna, Nico; Mehaut, Jean-François; Pouget, Kevin; Videau, Brice; Boyer, Eric; Allalen, Momme; Auweter, Axel; Brayford, David; Tafani, Daniele; Weinberg, Volker; Brömmel, Dirk; Halver, René; Meinke, Jan H.; Beivide Palacio, Ramon; Benito, Mariano; Vallejo, Enrique; Valero Cortés, Mateo; Ramirez, Alex (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    High-performance computing (HPC) is recognized as one of the pillars for further progress in science, industry, medicine, and education. Current HPC systems are being developed to overcome emerging architectural challenges ...
  • Throughput unfairness in Dragonfly networks under realistic traffic patterns 

    Fuentes, Pablo; Vallejo, Enrique; Camarero, Cristóbal; Beivide Palacio, Ramon; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2015)
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    Dragonfly networks have a two-level hierarchical arrangement of the network routers, and allow for a competitive cost-performance solution in large systems. Non-minimal adaptive routing is employed to fully exploit the ...
  • Towards fair, scalable, locking 

    Vallejo, Enrique; Sanyal, Sutirtha; Harris, Tim; Vallejo, Fernando; Beivide Palacio, Ramon; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2008)
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    Without care, Hardware Transactional Memory presents several performance pathologies that can degrade its performance. Among them, writers of commonly read variables can suffer from starvation. Though different solutions ...