Now showing items 1-3 of 3

  • An analyzable memory controller for hard real-time CMPs 

    Paolieri, Marco; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (2010-02-05)
    Article
    Open Access
    Multicore processors (CMPs) represent a good solution to provide the performance required by current and future hard real-time systems. However, it is difficult to compute a tight WCET estimation for CMPs due to interferences ...
  • RVC: A mechanism for time-analyzable real-time processors with faulty caches 

    Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Sazeides, Yanos; Valero Cortés, Mateo (2011)
    Conference report
    Restricted access - publisher's policy
    Geometry scaling due to technology evolution as well as Vcc scaling lead to failures in large SRAM arrays such as caches. Faulty bits can be tolerated from the average performance perspective, but make critical realtime ...
  • Using randomized caches in probabilistic real-time systems 

    Quiñones, Eduardo; Berger, Emery D.; Bernat, Guillem; Cazorla Almeida, Francisco Javier (2009)
    Conference report
    Restricted access - publisher's policy
    While hardware caches are generally effective at improving application performance, they greatly complicate performance prediction. Slight changes in memory layout or data access patterns can lead to large and ...