Now showing items 1-14 of 14

  • An abstraction methodology for the evaluation of multi-core multi-threaded architectures 

    Zilan, Ruken; Verdú Mulà, Javier; García Vidal, Jorge; Nemirovsky, Mario; Milito, Rodolfo; Valero Cortés, Mateo (IEEE Computer Society Publications, 2011)
    Conference report
    Restricted access - publisher's policy
    As the evolution of multi-core multi-threaded processors continues, the complexity demanded to perform an extensive trade-off analysis, increases proportionally. Cycle-accurate or trace-driven simulators are too slow to ...
  • Area and laser power scalability analysis in photonic networks-on-chip 

    Abadal Cavallé, Sergi; Cabellos Aparicio, Alberto; Lázaro Villa, José Antonio; Nemirovsky, Mario; Alarcón Cot, Eduardo José; Solé Pareta, Josep (Institute of Electrical and Electronics Engineers (IEEE), 2013)
    Conference lecture
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    In the last decade, the field of microprocessor architecture has seen the rise of multicore processors, which consist of the interconnection of a set of independent processing units or cores in the same chip. As the number ...
  • Characterizing the resource-sharing levels of the UltraSparc T2 processor 

    Cakarevic, Vladimir; Radojkovic, Petar; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2009)
    Conference report
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    Thread level parallelism (TLP) has become a popular trend to improve processor performance, overcoming the limitations of extracting instruction level parallelism. Each TLP paradigm, such as Simultaneous Multithreading or ...
  • Graphene-enabled wireless communication for massive multicore architectures 

    Abadal Cavallé, Sergi; Alarcón Cot, Eduardo José; Cabellos Aparicio, Alberto; Lemme, Max; Nemirovsky, Mario (2013-11-11)
    Article
    Restricted access - publisher's policy
    Current trends in microprocessor architecture design are leading towards a dramatic increase of core-level parallelization, wherein a given number of independent processors or cores are interconnected. Since the main ...
  • Improving the energy efficiency of hardware-assisted watchpoint systems 

    Karakostas, Vasileios; Tomić, Saša; Unsal, Osman Sabri; Nemirovsky, Mario; Cristal Kestelman, Adrián (2013)
    Conference report
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    Hardware-assisted watchpoint systems enhance the execution of numerous dynamic software techniques, such as memory protection, module isolation, deterministic execution, and data race detection. In this paper, we show ...
  • Internet traffic and the behavior of processing workloads 

    Zilan, Ruken; Verdú Mulà, Javier; García Vidal, Jorge; Nemirovsky, Mario; Valero Cortés, Mateo (2009-06)
    Conference report
    Open Access
    Nowadays, the evolution of network services provided at the edge of Internet increases the requirements of network applications. Such applications result in complexities thus, the processors need to execute more complex ...
  • Measuring operating system overhead on CMT processors 

    Radojkovic, Petar; Cakarevic, Vladimir; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Gioiosa, Roberto; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo (IEEE Computer Society Publications, 2008)
    Conference report
    Open Access
    Numerous studies have shown that Operating System (OS) noise is one of the reasons for significant performance degradation in clustered architectures. Although many studies examine the OS noise for High Performance Computing ...
  • Measuring operating system overhead on Sun UltraSparc T1 processor 

    Radojkovic, Petar; Cakarevic, Vladimir; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Gioiosa, Roberto; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo (2009-06)
    Conference report
    Open Access
    Numerous studies have shown that Operating System (OS) noise is one of the reasons for significant performance degradation in clustered architectures. Although many studies examine the OS noise for High Performance Computing, ...
  • On the area and energy scalability of wireless network-on-chip: a model-based benchmarked design space exploration 

    Abadal Cavallé, Sergi; Iannazzo Soteras, Mario Enrique; Nemirovsky, Mario; Cabellos Aparicio, Alberto; Lee, Heekwan; Alarcón Cot, Eduardo José (2014-07-02)
    Article
    Open Access
    Networks-on-Chip (NoCs) are emerging as the way to interconnect the processing cores and the memory within a chip multiprocessor. As recent years have seen a significant increase in the number of cores per chip, it is ...
  • Overhead of the spin-lock loop in UltraSPARC T2 

    Cakarevic, Vladimir; Radojkovic, Petar; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Nemirovsky, Mario; Valero Cortés, Mateo; Pajuelo González, Manuel Alejandro; Verdú Mulà, Javier (2008-06-04)
    Conference report
    Open Access
    Spin locks are task synchronization mechanism used to provide mutual exclusion to shared software resources. Spin locks have a good performance in several situations over other synchronization mechanisms, i.e., when on ...
  • Thread to strand binding of parallel network applications in massive multi-threaded systems 

    Radojkovic, Petar; Cakarevic, Vladimir; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo (2010-05)
    Article
    Restricted access - publisher's policy
    In processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a single level of resource sharing, such as pure-SMT ...
  • Thread to strand binding of parallel network applications in massive multi-threaded systems 

    Radojkovic, Petar; Cakarevic, Vladimir; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo (ACM Press. Association for Computing Machinery, 2010-01)
    Conference report
    Restricted access - publisher's policy
    In processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a single level of resource sharing, such as pure-SMT ...
  • Understanding the overhead of the spin-lock loop in CMT architectures 

    Cakarevic, Vladimir; Radojkovic, Petar; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Gioiosa, Roberto; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo (2008)
    Conference report
    Open Access
    Abstract—Spin locks are a synchronization mechanisms used to provide mutual exclusion to shared software resources. Spin locks are used over other synchronization mechanisms in several situations, like when the average ...
  • Undertanding the overhead of the spin-lock loop in CMT architectures 

    Cakarevic, Vladimir; Radojkovic, Petar; Verdú Mulà, Javier; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Pajuelo González, Manuel Alejandro; Nemirovsky, Mario; Valero Cortés, Mateo (2008)
    Conference report
    Open Access
    Spin locks are a synchronization mechanisms used to provide mutual exclusion to shared software resources. Spin locks are used over other synchronization mechanisms in several situations, like when the average waiting ...