Ara es mostren els items 1-20 de 25

  • An abstraction methodology for the evaluation of multi-core multi-threaded architectures 

    Zilan, Ruken; Verdú Mulà, Javier; García Vidal, Jorge; Nemirovsky, Mario; Milito, Rodolfo; Valero Cortés, Mateo (IEEE Computer Society Publications, 2011)
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    As the evolution of multi-core multi-threaded processors continues, the complexity demanded to perform an extensive trade-off analysis, increases proportionally. Cycle-accurate or trace-driven simulators are too slow to ...
  • Area and laser power scalability analysis in photonic networks-on-chip 

    Abadal Cavallé, Sergi; Cabellos Aparicio, Alberto; Lázaro Villa, José Antonio; Nemirovsky, Mario; Alarcón Cot, Eduardo José; Solé Pareta, Josep (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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    In the last decade, the field of microprocessor architecture has seen the rise of multicore processors, which consist of the interconnection of a set of independent processing units or cores in the same chip. As the number ...
  • Broadcast-enabled massive multicore architectures: a wireless RF approach 

    Abadal Cavallé, Sergi; Sheinman, Benny; Katz, Oded; Markish, Ofer; Elad, Danny; Fournier, Yvan; Roca, Damian; Hanzich, Mauricio; Houzeaux, Guillaume; Nemirovsky, Mario; Alarcón Cot, Eduardo José; Cabellos Aparicio, Alberto (2015-09)
    Article
    Accés obert
    Broadcast traditionally has been regarded as a prohibitive communication transaction in multiprocessor environments. Nowadays, such a constraint largely drives the design of architectures and algorithms all-pervasive in ...
  • Characterizing the resource-sharing levels of the UltraSparc T2 processor 

    Cakarevic, Vladimir; Radojkovic, Petar; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2009)
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    Thread level parallelism (TLP) has become a popular trend to improve processor performance, overcoming the limitations of extracting instruction level parallelism. Each TLP paradigm, such as Simultaneous Multithreading or ...
  • Disaggregated Computing. An Evaluation of Current Trends for Datacentres 

    Meyer, Hugo; Sancho, Jose C.; Quiroga, Josue V.; Zyulkyarov, Ferad; Roca, Damian; Nemirovsky, Mario (Elsevier, 2017)
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    Next generation data centers will likely be based on the emerging paradigm of disaggregated function-blocks-as-a-unit departing from the current state of mainboard-as-a-unit. Multiple functional blocks or bricks such as ...
  • Emergent behaviors in the Internet of things: The ultimate ultra-large-scale system 

    Roca, Damian; Nemirovsky, Daniel; Nemirovsky, Mario; Milito, Rodolfo; Valero Cortés, Mateo (2016-11)
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    To reach its potential, the Internet of Things (IoT) must break down the silos that limit applications' interoperability and hinder their manageability. Doing so leads to the building of ultra-large-scale systems (ULSS) ...
  • Fog function virtualization: A flexible solution for IoT applications 

    Roca, Damian; Quiroga, Josue V.; Valero Cortés, Mateo; Nemirovsky, Mario (Institute of Electrical and Electronics Engineers (IEEE), 2017)
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    The Internet of Things applications must carefully assess certain crucial factors such as the real-time and largely distributed nature of the “things”. Fog Computing provides an architecture to satisfy those requirements ...
  • Graphene-enabled wireless communication for massive multicore architectures 

    Abadal Cavallé, Sergi; Alarcón Cot, Eduardo José; Cabellos Aparicio, Alberto; Lemme, Max; Nemirovsky, Mario (2013-11-11)
    Article
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    Current trends in microprocessor architecture design are leading towards a dramatic increase of core-level parallelization, wherein a given number of independent processors or cores are interconnected. Since the main ...
  • Improving the energy efficiency of hardware-assisted watchpoint systems 

    Karakostas, Vasileios; Tomić, Saša; Unsal, Osman Sabri; Nemirovsky, Mario; Cristal Kestelman, Adrián (2013)
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    Hardware-assisted watchpoint systems enhance the execution of numerous dynamic software techniques, such as memory protection, module isolation, deterministic execution, and data race detection. In this paper, we show ...
  • Internet traffic and the behavior of processing workloads 

    Zilan, Ruken; Verdú Mulà, Javier; García Vidal, Jorge; Nemirovsky, Mario; Valero Cortés, Mateo (2009-06)
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    Nowadays, the evolution of network services provided at the edge of Internet increases the requirements of network applications. Such applications result in complexities thus, the processors need to execute more complex ...
  • Measuring operating system overhead on CMT processors 

    Radojkovic, Petar; Cakarevic, Vladimir; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Gioiosa, Roberto; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo (IEEE Computer Society Publications, 2008)
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    Numerous studies have shown that Operating System (OS) noise is one of the reasons for significant performance degradation in clustered architectures. Although many studies examine the OS noise for High Performance Computing ...
  • Measuring operating system overhead on Sun UltraSparc T1 processor 

    Radojkovic, Petar; Cakarevic, Vladimir; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Gioiosa, Roberto; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo (2009-06)
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    Numerous studies have shown that Operating System (OS) noise is one of the reasons for significant performance degradation in clustered architectures. Although many studies examine the OS noise for High Performance Computing, ...
  • NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs 

    Seyedi, Azam; Karakostas, Vasileios; Cosemans, Stefan; Cristal, Adrian; Nemirovsky, Mario; Unsal, Osman (Institute of Electrical and Electronics Engineers (IEEE), 2015-07-10)
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    In this paper we propose a novel Content Addressable Memory (CAM) cell, NEMsCAM, based on both Nano-electro-mechanical (NEM) switches and CMOS technologies. The memory component of the proposed CAM cell is designed with ...
  • Networking challenges and prospective impact of broadcast-oriented wireless networkson- chip 

    Abadal Cavallé, Sergi; Nemirovsky, Mario; Alarcón Cot, Eduardo José; Cabellos Aparicio, Alberto (Association for Computing Machinery (ACM), 2015)
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    The cost of broadcast has been constraining the design of manycore processors and of the algorithms that run upon them. However, as on-chip RF technologies allow the design of small-footprint and high-bandwidth antennas ...
  • On the area and energy scalability of wireless network-on-chip: a model-based benchmarked design space exploration 

    Abadal Cavallé, Sergi; Iannazzo Soteras, Mario Enrique; Nemirovsky, Mario; Cabellos Aparicio, Alberto; Lee, Heekwan; Alarcón Cot, Eduardo José (2014-07-02)
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    Networks-on-Chip (NoCs) are emerging as the way to interconnect the processing cores and the memory within a chip multiprocessor. As recent years have seen a significant increase in the number of cores per chip, it is ...
  • Overhead of the spin-lock loop in UltraSPARC T2 

    Cakarevic, Vladimir; Radojkovic, Petar; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Nemirovsky, Mario; Valero Cortés, Mateo; Pajuelo González, Manuel Alejandro; Verdú Mulà, Javier (2008-06-04)
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    Spin locks are task synchronization mechanism used to provide mutual exclusion to shared software resources. Spin locks have a good performance in several situations over other synchronization mechanisms, i.e., when on ...
  • Scalability of broadcast performance in wireless network-on-chip 

    Abadal Cavallé, Sergi; Mestres Sugrañes, Albert; Nemirovsky, Mario; Lee, Heekwan; González Colás, Antonio María; Alarcón Cot, Eduardo José; Cabellos Aparicio, Alberto (2016-12-01)
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    Accés obert
    Networks-on-Chip (NoCs) are currently the paradigm of choice to interconnect the cores of a chip multiprocessor. However, conventional NoCs may not suffice to fulfill the on-chip communication requirements of processors ...
  • Scalability of Broadcast Performance in Wireless Network-on-Chip 

    Abadal, Sergi; Mestres, Albert; Nemirovsky, Mario; Lee, Heekwan; Gonzalez, Antonio; Alarcón, Eduard; Cabellos-Aparicio, Albert (IEEE, 2016-12-01)
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    Accés obert
    Networks-on-Chip (NoCs) are currently the paradigm of choice to interconnect the cores of a chip multiprocessor. However, conventional NoCs may not suffice to fulfill the on-chip communication requirements of processors ...
  • Tackling IoT ultra large scale systems: Fog computing in support of hierarchical emergent behaviors 

    Roca, Damian; Milito, Rodolfo; Nemirovsky, Mario; Valero Cortés, Mateo (Springer, 2018)
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    The Internet of Things (IoT) marks a phase transition in the evolution of the Internet, distinguished by a massive connectivity and the interaction with the physical world. The organic evolution of IoT requires the ...
  • Thread assignment in multicore/multithreaded processors: A statistical approach 

    Radojkovic, Petar; Carpenter, Paul M.; Moreto Planas, Miquel; Cakarevic, Vladimir; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo (2016-01-01)
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    Accés obert
    The introduction of multicore/multithreaded processors, comprised of a large number of hardware contexts (virtual CPUs) that share resources at multiple levels, has made process scheduling, in particular assignment of ...