Exploració per autor "Ginosar, Ran"
Ara es mostren els items 1-3 de 3
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CAD directions for high performance asynchronous circuits
Stevens, Kenneth S.; Rotem, Shai; Burns, Steven M.; Cortadella, Jordi; Ginosar, Ran; Kishinevsky, Michael; Roncken, Marly (Association for Computing Machinery (ACM), 1999)
Text en actes de congrés
Accés obertThis paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using relative timing. This methodology was developed for a prototype iA32 ... -
Metastability in better-than-worst-case designs
Beer, Salomon; Cannizzaro, Marco; Cortadella, Jordi; Ginosar, Ran; Lavagno, Luciano (Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés obertBetter-Than-Worst-Case-Designs use timing speculation to run with a cycle period faster than the one required for worst-case conditions. This speculation may produce timing violations and metastability that result in ... -
SafeRazor: Metastability-robust adaptive clocking in resilient circuits
Cannizzaro, Marco; Beer, Salomon; Cortadella, Jordi; Ginosar, Ran; Lavagno, Luciano (2015-09-01)
Article
Accés obertRazor-based circuits can run faster or at a lower voltage than those designed to work at the worst case corner. However, all known implementations are prone to failures due to the non-deterministic timing behavior introduced ...