Now showing items 1-3 of 3

  • A polymorphic register file for matrix operations 

    Ciobanu, Catalin; Kuzmanov, Georgi; Gaydadjiev, Georgi; Ramírez Bellido, Alejandro (IEEE Computer Society Publications, 2010)
    Conference report
    Open Access
    Previous vector architectures divided the available register file space in a fixed number of registers of equal sizes and shapes. We propose a register file organization which allows dynamic creation of a variable number ...
  • Scalability evaluation of a polymorphic register file: a CG case study 

    Ciobanu, Catalin; Martorell Bofill, Xavier; Kuzmanov, Georgi; Ramírez Bellido, Alejandro; Gaydadjiev, Georgi (Springer, 2011)
    Conference report
    Restricted access - publisher's policy
    We evaluate the scalability of a Polymorphic Register File using the Conjugate Gradient method as a case study. We focus on a heterogeneous multi-processor architecture, taking into consideration critical parameters such ...
  • The SARC architecture 

    Gaydadjiev, Georgi; Isaza, Sebastian; Ramírez Bellido, Alejandro; Cabarcas, Felipe; Juurlink, Ben; Álvarez Mesa, Mauricio; Sánchez Castaño, Friman; Azevedo, Arnaldo; Meenderinck, Cor; Ciobanu, Catalin (2010-10)
    Article
    Open Access
    The SARC architecture is composed of multiple processor types and a set of user-managed direct memory access (DMA) engines that let the runtime scheduler overlap data transfer and computation. The runtime system automatically ...