• Rebalancing the core front-end through HPC code analysis 

    Milic, Ugljesa; Carpenter, Paul; Rico, Alejandro; Ramirez, Alex (IEEE, 2016-10-10)
    Text en actes de congrés
    Accés obert
    There is a need to increase performance under the same power and area envelope to achieve Exascale technology in high performance computing (HPC). The today's chip multiprocessor (CMP) design is tailored by traditional ...
  • RETHINK big: European roadmap for hardware anc networking optimizations for big data 

    Alioto, Gina; Carpenter, Paul; Cristal, Adrian; Unsal, Osman; Leich, Marcus; Avare, Christophe (Institute of Electrical and Electronics Engineers (IEEE), 2017-05-15)
    Comunicació de congrés
    Accés obert
    This paper discusses the results of the RETHINK big Project, a 2-year Collaborative Support Action funded by the European Commission in order to write the European Roadmap for Hardware and Networking optimizations for Big ...
  • Sharing the instruction cache among lean cores on an asymmetric CMP for HPC applications 

    Milic, Ugljesa; Rico, Alejandro; Carpenter, Paul; Ramirez, Alex (Institute of Electrical and Electronics Engineers (IEEE), 2017-07-13)
    Comunicació de congrés
    Accés obert
    High performance computing (HPC) applications have parallel code sections that must scale to large numbers of cores, which makes them sensitive to serial regions. Current supercomputing systems with heterogeneous or ...