Exploració per autor "Buyuktosunoglu, Alper"

Ara es mostren els items 1-9 de 9

    • Adaptive power shifting for power-constrained heterogeneous systems 

      Ortega Carrasco, Cristobal; Alvarez Martí, Lluc; Buyuktosunoglu, Alper; Bertran Monfort, Ramon; Rosedahl, Todd Jon; Bose, Pradip; Moretó Planas, Miquel (Institute of Electrical and Electronics Engineers (IEEE), 2023-03-01)
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      The number and heterogeneity of compute devices, even within a single compute node, has been steadily on the rise. Since all systems must operate under a power cap, the number of discrete devices that can run simultaneously ...

    • CPU accounting in CMP processors 

      Luque, Carlos; Moretó Planas, Miquel; Cazorla, Francisco; Gioiosa, Roberto; Buyuktosunoglu, Alper; Valero Cortés, Mateo (2009-01)
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      Chip-MultiProcessors (CMP) introduce complexities when accounting CPU utilization to processes because the progress done by a process during an interval of time highly depends on the activity of the other processes it is ...

    • Increasing multicore system efficiency through intelligent bandwidth shifting 

      Jiménez, Víctor; Buyuktosunoglu, Alper; Bose, Pradip; O'Connell, Francis P.; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2015)
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      Memory bandwidth is a crucial resource in computing systems. Current CMP/SMT processors have a significant number of cores and they can run many threads concurrently. This large thread count adds high pressure to the memory ...

    • Intelligent adaptation of hardware knobs for improving performance and power consumption 

      Ortega Carrasco, Cristobal; Álvarez Martí, Lluc; Casas, Marc; Bertran, Ramon; Buyuktosunoglu, Alper; Eichenberger, Alexandre; Bose, Pradip; Moretó Planas, Miquel (Institute of Electrical and Electronics Engineers (IEEE), 2021-01-01)
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      Current microprocessors include several knobs to modify the hardware behavior in order to improve performance, power, and energy under different workload demands. An impractical and time consuming offline profiling is ...

    • ITCA: Inter-Task Conflict-Aware CPU accounting for CMPs 

      Luque, Carlos; Moretó Planas, Miquel; Cazorla, Francisco; Gioiosa, Roberto; Buyuktosunoglu, Alper; Valero Cortés, Mateo (IEEE Computer Society, 2009)
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      Chip-MultiProcessor (CMP) architectures are becoming more and more popular as an alternative to the traditional processors that only extract instruction-level parallelism from an application. CMPs introduce complexities ...

    • ITCA: inter-task conflict-aware CPU accounting for CMPs 

      Luque, Carlos; Moretó Planas, Miquel; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Buyuktosunoglu, Alper; Valero Cortés, Mateo (IEEE Computer Society Publications, 2009)
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    • libPRISM: an intelligent adaptation of prefetch and SMT levels 

      Ortega, Cristobal; Moretó Planas, Miquel; Casas, Marc; Bertran, Ramon; Buyuktosunoglu, Alper; Eichenberger, Alexandre; Bose, Pradip (Association for Computing Machinery (ACM), 2017)
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      Current microprocessors include several knobs to modify the hardware behavior in order to improve performance under different workload demands. An impractical and time consuming offline profiling is needed to evaluate the ...

    • Software-controlled priority characterization of POWER5 processor 

      Boneti, Carlos; Cazorla, Francisco; Gioiosa, Roberto; Buyuktosunoglu, Alper; Cher, Chen-Yong; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
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      Due to the limitations of instruction-level parallelism, thread-level parallelism has become a popular way to improve processor performance. One example is the IBM POWER5TM processor, a two-context simultaneous-multithreaded ...

    • Systematic energy characterization of CMP/SMT processor systems via automated micro-benchmarks 

      Bertrán, Ramon; Buyuktosunoglu, Alper; Gupta, Meeta S.; González Tallada, Marc; Bose, Pradip (2012)
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      Microprocessor-based systems today are composed of multi-core, multi-threaded processors with complex cache hierarchies and gigabytes of main memory. Accurate characterization of such a system, through predictive pre-silicon ...