Ara es mostren els items 25-39 de 39

  • On the convergence of mainstream and mission-critical markets 

    Girbal, Sylvain; Moreto Planas, Miquel; Grasset, Arnaud; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Yehia, Sami (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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    The computing market has been dominated during the last two decades by the well-known convergence of the highperformance computing market and the mobile market. In this paper we witness a new type of convergence between ...
  • Probabilistic timing analysis on conventional cache designs 

    Kosmidis, Leonidas; Curtsinger, Charlie; Quiñones, Eduardo; Abella Ferrer, Jaume; Berger, Emery D.; Cazorla Almeida, Francisco Javier (2013)
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    Probabilistic timing analysis (PTA), a promising alternative to traditional worst-case execution time (WCET) analyses, enables pairing time bounds (named probabilistic WCET or pWCET) with an exceedance probability (e.g., ...
  • Probabilistic timing analysis on time-randomized platforms for the space domain 

    Fernandez, Mikel; Morales, David; Kosmidis, Leonidas; Bardizbanyan, Alen; Broster, Ian; Hernandez, Carles; Quiñones, Eduardo; Abella, Jaume; Cazorla, Francisco; Machado, Paulo; Fossati, Luca (Institute of Electrical and Electronics Engineers (IEEE), 2017-05-15)
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    Timing Verification is a fundamental step in real-time embedded systems, with measurement-based timing analysis (MBTA) being the most common approach used to that end. We present a Space case study on a real platform that ...
  • PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis 

    Cazorla, Francisco J.; Abella, Jaume; Andersson, Jan; Vardanega, Tullio; Vatrinet, Francis; Bate, Iain; Broster, Ian; Azkarate-askasua, Mikel; Wartel, Franck; Cucu, Liliana; Cros, Fabrice; Farrall, Glenn; Gogonel, Adriana; Gianarro, Andrea; Triquet, Benoit; Hernandez, Carles; Lo, Code; Maxim, Cristian; Morales, David; Quiñones, Eduardo; Mezzetti, Enrico; Kosmidis, Leonidas; Aguirre, Irune; Fernandez, Mikel; Slijepcevic, Mladen; Conmy, Philippa; Talaboulma, Walid (IEEE, 2016-08-31)
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    The use of increasingly complex hardware and software platforms in response to the ever rising performance demands of modern real-time systems complicates the verification and validation of their timing behaviour, which ...
  • pTNoC: Probabilistically time-analyzable tree-based NoC for mixed-criticality systems 

    Slijepcevic, Mladen; Fernández, Mikel; Hernández, Carles; Abella, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    The use of networks-on-chip (NoC) in real-time safety-critical multicore systems challenges deriving tight worst-case execution time (WCET) estimates. This is due to the complexities in tightly upper-bounding the contention ...
  • Response-time analysis of DAG tasks under fixed priority scheduling with limited preemptions 

    Serrano, Maria A.; Melani, Alessandra; Bertogna, Marko; Quiñones, Eduardo (Institute of Electrical and Electronics Engineers (IEEE), 2016-03-14)
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    Limited preemptive (LP) scheduling has been demonstrated to effectively improve the schedulability of fully preemptive (FP) and fully non-preemptive (FNP) paradigms. On one side, LP reduces the preemption related overheads ...
  • RunPar: An allocation algorithm for automotive applications exploiting runnable parallelism in multicores 

    Panic, Milos; Kehr, Sebastian; Quiñones, Eduardo; Boddecker, Bert; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2014)
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    Automotive applications increasingly rely on AUTOSAR for their design and execution. AUTOSAR applications comprise functions, called runnables, that are grouped into AUTOSAR tasks. Tasks are the unit of scheduling (UoS) ...
  • RVC: A mechanism for time-analyzable real-time processors with faulty caches 

    Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Sazeides, Yanos; Valero Cortés, Mateo (2011)
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    Geometry scaling due to technology evolution as well as Vcc scaling lead to failures in large SRAM arrays such as caches. Faulty bits can be tolerated from the average performance perspective, but make critical realtime ...
  • Seeking time-composable partitions of tasks for COTS multicore processors 

    Fernández, Gabriel; Abella Ferrer, Jaume; Quiñones, Eduardo; Fossati, Luca; Zulianello, Marco; Vardanega, Tullio; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2015)
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    The timing verification of real-time single core systems involves a timing analysis step that yields an Execution Time Bound (ETB) for each task, followed by a schedulability analysis step, where the scheduling attributes ...
  • Supertask: Maximizing runnable-level parallelism in AUTOSAR applications 

    Kehr, Sebastian; Panic, Milos; Quiñones, Eduardo; Boddeker, Bert; Becerril Sandoval, Jorge; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier; Schäfer, Günter (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    The migration of legacy AUTOSAR automotive software from a single-core ECU to a multicore ECU faces two main challenges: 1) data dependencies between AUTOSAR runnables must be respected, which may limit the level of ...
  • TASA: toolchain-agnostic static software randomisation for critical real-time systems 

    Kosmidis, Leonidas; Vargas, Roberto; Morales, David; Quiñones, Eduardo; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2016)
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    Measurement-Based Probabilistic Timing Analysis (MBPTA) derives WCET estimates for tasks running on processors comprising high-performance features such as caches. MBPTA's correct application requires the system to exhibit ...
  • The next convergence: High-performance and mission-critical markets 

    Girbal, Sylvain; Moreto Planas, Miquel; Grasset, Arnaud; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Yehia, Sami (2013)
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    The well-known convergence of the high-performance computing and the mobile markets has been a dominating factor in the computing market during the last two decades. In this paper we witness a new type of convergence between ...
  • Time-analysable non-partitioned shared caches for real-time multicore systems 

    Slijepcevic, Mladen; Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2014)
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    Shared caches in multicores challenge Worst-Case Execution Time (WCET) estimation due to inter-task interferences. Hard-ware and software cache partitioning address this issue although they complicate data sharing among ...
  • Timing verification of fault-tolerant chips for safety-critical applications in harsh environments 

    Slijepcevic, Mladen; Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla, Francisco J. (2014-11-01)
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    Critical real-time embedded systems feature complex safety-related, performance-demanding functionality. High-performance hardware and software can provide such functionality, but the use of aggressive technologies and ...
  • Using randomized caches in probabilistic real-time systems 

    Quiñones, Eduardo; Berger, Emery D.; Bernat, Guillem; Cazorla Almeida, Francisco Javier (2009)
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    While hardware caches are generally effective at improving application performance, they greatly complicate performance prediction. Slight changes in memory layout or data access patterns can lead to large and ...