Ara es mostren els items 19-38 de 44

  • Improving branch prediction and predicated execution in out-of-order processors 

    Quiñones, Eduardo; Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2007)
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    If-conversion is a compiler technique that reduces the misprediction penalties caused by hard-to-predict branches, transforming control dependencies into data dependencies. Although it is globally beneficial, it has a ...
  • Improving performance guarantees in wormhole mesh NoC designs 

    Panic, Milos; Hernández, Carles; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    Wormhole-based mesh Networks-on-Chip (wNoC) are deployed in high-performance many-core processors due to their physical scalability and low-cost. Delivering tight and time composable Worst-Case Execution Time (WCET) estimates ...
  • Leveraging register windows to reduce physical registers to the bare minimum 

    Quiñones, Eduardo; Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (2010-12)
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    Register window is an architectural technique that reduces memory operations required to save and restore registers across procedure calls. Its effectiveness depends on the size of the register file. Such register requirements ...
  • Measurement-based probabilistic timing analysis for multi-path programs 

    Cucu Grosjean, Liliana; Santinelli, Luca; Houston, Michael; Lo, Code; Vardanega, Tulio; Kosmidis, Leonidas; Abella Ferrer, Jaume; Mezzetti, Enrico; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (2012)
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    The rigorous application of static timing analysis requires a large and costly amount of detail knowledge on the hardware and software components of the system. Probabilistic Timing Analysis has potential for reducing the ...
  • Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case study 

    Wartel, Franck; Kosmidis, Leonidas; Lo, Code; Triquet, Benoit; Quiñones, Eduardo; Abella Ferrer, Jaume; Gogonel, Adriana; Baldovin, Andrea; Mezzetti, Enrico; Cucu Grosjean, Liliana; Vardanega, Tulio; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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    Probabilistic Timing Analysis (PTA) in general and its measurement-based variant called MBPTA in particular can mitigate some of the problems that impair current worst-case execution time (WCET) analysis techniques. MBPTA ...
  • Measurement-based timing analysis of the AURIX caches 

    Kosmidis, Leonidas; Compagnin, Davide; Morales, David; Mezzetti, Enrico; Quiñones, Eduardo; Abella Ferrer, Jaume; Vardanega, Tullio; Cazorla Almeida, Francisco Javier (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2016)
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    Cache memories are one of the hardware resources with higher potential to reduce worst-case execution time (WCET) costs for software programs with tight real-time constraints. Yet, the complexity of cache analysis has ...
  • Modeling high-performance wormhole NoCs for critical real-time embedded systems 

    Panic, Milos; Hernández, Carles; Quiñones, Eduardo; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    Manycore chips are a promising computing platform to cope with the increasing performance needs of critical real-time embedded systems (CRTES). However, manycores adoption by CRTES industry requires understanding task's ...
  • Modelling the confidence of timing analysis for time randomised caches 

    Benedicte Illescas, Pedro; Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    Timing is a key non-functional property in embedded real-Time systems (ERTS). ERTS increasingly require higher levels of performance that can only be sensibly provided by deploying high-performance hardware, which however ...
  • Multi-level unified caches for probabilistically time analysable real-time systems 

    Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (IEEEXPLORE, 2013)
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    Caches are key resources in high-end processor architectures to increase performance. In fact, most high-performance processors come equipped with a multi-level cache hierarchy. In terms of guaranteed performance, however, ...
  • On the convergence of mainstream and mission-critical markets 

    Girbal, Sylvain; Moreto Planas, Miquel; Grasset, Arnaud; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Yehia, Sami (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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    The computing market has been dominated during the last two decades by the well-known convergence of the highperformance computing market and the mobile market. In this paper we witness a new type of convergence between ...
  • Parcus: Energy-Aware and Robust Parallelization of AUTOSAR Legacy Applications 

    Kehr, Sebastian; Quiñones, Eduardo; Langen, Dominik; Böddeker, Bert; Schäfer, Günter (Institute of Electrical and Electronics Engineers (IEEE), 2017-06-08)
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    Embedded multicore processors are an attractive alternative to sophisticated single-core processors for the use in automobile electronic control units (ECUs), due to their expected higher performance and energy efficiency. ...
  • Probabilistic timing analysis on conventional cache designs 

    Kosmidis, Leonidas; Curtsinger, Charlie; Quiñones, Eduardo; Abella Ferrer, Jaume; Berger, Emery D.; Cazorla Almeida, Francisco Javier (2013)
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    Probabilistic timing analysis (PTA), a promising alternative to traditional worst-case execution time (WCET) analyses, enables pairing time bounds (named probabilistic WCET or pWCET) with an exceedance probability (e.g., ...
  • Probabilistic timing analysis on time-randomized platforms for the space domain 

    Fernandez, Mikel; Morales, David; Kosmidis, Leonidas; Bardizbanyan, Alen; Broster, Ian; Hernandez, Carles; Quiñones, Eduardo; Abella, Jaume; Cazorla, Francisco; Machado, Paulo; Fossati, Luca (Institute of Electrical and Electronics Engineers (IEEE), 2017-05-15)
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    Timing Verification is a fundamental step in real-time embedded systems, with measurement-based timing analysis (MBTA) being the most common approach used to that end. We present a Space case study on a real platform that ...
  • PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis 

    Cazorla, Francisco J.; Abella, Jaume; Andersson, Jan; Vardanega, Tullio; Vatrinet, Francis; Bate, Iain; Broster, Ian; Azkarate-askasua, Mikel; Wartel, Franck; Cucu, Liliana; Cros, Fabrice; Farrall, Glenn; Gogonel, Adriana; Gianarro, Andrea; Triquet, Benoit; Hernandez, Carles; Lo, Code; Maxim, Cristian; Morales, David; Quiñones, Eduardo; Mezzetti, Enrico; Kosmidis, Leonidas; Aguirre, Irune; Fernandez, Mikel; Slijepcevic, Mladen; Conmy, Philippa; Talaboulma, Walid (IEEE, 2016-08-31)
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    The use of increasingly complex hardware and software platforms in response to the ever rising performance demands of modern real-time systems complicates the verification and validation of their timing behaviour, which ...
  • pTNoC: Probabilistically time-analyzable tree-based NoC for mixed-criticality systems 

    Slijepcevic, Mladen; Fernández, Mikel; Hernández, Carles; Abella, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    The use of networks-on-chip (NoC) in real-time safety-critical multicore systems challenges deriving tight worst-case execution time (WCET) estimates. This is due to the complexities in tightly upper-bounding the contention ...
  • Response-time analysis of DAG tasks under fixed priority scheduling with limited preemptions 

    Serrano, Maria A.; Melani, Alessandra; Bertogna, Marko; Quiñones, Eduardo (Institute of Electrical and Electronics Engineers (IEEE), 2016-03-14)
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    Limited preemptive (LP) scheduling has been demonstrated to effectively improve the schedulability of fully preemptive (FP) and fully non-preemptive (FNP) paradigms. On one side, LP reduces the preemption related overheads ...
  • RunPar: An allocation algorithm for automotive applications exploiting runnable parallelism in multicores 

    Panic, Milos; Kehr, Sebastian; Quiñones, Eduardo; Boddecker, Bert; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2014)
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    Automotive applications increasingly rely on AUTOSAR for their design and execution. AUTOSAR applications comprise functions, called runnables, that are grouped into AUTOSAR tasks. Tasks are the unit of scheduling (UoS) ...
  • RVC: A mechanism for time-analyzable real-time processors with faulty caches 

    Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Sazeides, Yanos; Valero Cortés, Mateo (2011)
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    Geometry scaling due to technology evolution as well as Vcc scaling lead to failures in large SRAM arrays such as caches. Faulty bits can be tolerated from the average performance perspective, but make critical realtime ...
  • Seeking time-composable partitions of tasks for COTS multicore processors 

    Fernández, Gabriel; Abella Ferrer, Jaume; Quiñones, Eduardo; Fossati, Luca; Zulianello, Marco; Vardanega, Tullio; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2015)
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    The timing verification of real-time single core systems involves a timing analysis step that yields an Execution Time Bound (ETB) for each task, followed by a schedulability analysis step, where the scheduling attributes ...
  • Supertask: Maximizing runnable-level parallelism in AUTOSAR applications 

    Kehr, Sebastian; Panic, Milos; Quiñones, Eduardo; Boddeker, Bert; Becerril Sandoval, Jorge; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier; Schäfer, Günter (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    The migration of legacy AUTOSAR automotive software from a single-core ECU to a multicore ECU faces two main challenges: 1) data dependencies between AUTOSAR runnables must be respected, which may limit the level of ...