Now showing items 1-2 of 2

  • Logic synthesis for manufacturability considering regularity and lithography printability 

    Machado, Lucas; Dal Bem, Vinicius; Moll Echeto, Francisco de Borja; Gómez Fernández, Sergio; Ribas, Renato P.; Reis, André Inacio (IEEE Computer Society Publications, 2013)
    Conference report
    Restricted access - publisher's policy
    This paper presents a novel yield model for integrated circuits manufacturing, considering lithography printability problems as a source of yield loss. The use of regular layouts can improve the printability of IC layouts, ...
  • Transistor sizing analysis of regular fabrics 

    Marranghello, Felipe S.; Dal Bem, Vinicius; Reis, André I.; Ribas, Renato P.; Moll Echeto, Francisco de Borja (2011)
    Conference report
    Open Access
    This paper presents an extensive transistor sizing analysis for regular transistor fabrics. Several evaluation methods have been exploited, such as DC simulations, ring oscillators and single-gate open chain structures. ...