Ara es mostren els items 25-44 de 57

  • Measurement-based probabilistic timing analysis for multi-path programs 

    Cucu Grosjean, Liliana; Santinelli, Luca; Houston, Michael; Lo, Code; Vardanega, Tulio; Kosmidis, Leonidas; Abella Ferrer, Jaume; Mezzetti, Enrico; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (2012)
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    The rigorous application of static timing analysis requires a large and costly amount of detail knowledge on the hardware and software components of the system. Probabilistic Timing Analysis has potential for reducing the ...
  • Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case study 

    Wartel, Franck; Kosmidis, Leonidas; Lo, Code; Triquet, Benoit; Quiñones, Eduardo; Abella Ferrer, Jaume; Gogonel, Adriana; Baldovin, Andrea; Mezzetti, Enrico; Cucu Grosjean, Liliana; Vardanega, Tulio; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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    Probabilistic Timing Analysis (PTA) in general and its measurement-based variant called MBPTA in particular can mitigate some of the problems that impair current worst-case execution time (WCET) analysis techniques. MBPTA ...
  • Modelling probabilistic cache representativeness in the presence of arbitrary access patterns 

    Milutinovic, Suzana; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    Measurement-Based Probabilistic Timing Analysis (MBPTA) is a promising powerful industry-friendly method to derive worst-case execution time (WCET) estimates as needed for critical real-time embedded systems. MBPTA performs ...
  • Modelling the confidence of timing analysis for time randomised caches 

    Benedicte Illescas, Pedro; Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    Timing is a key non-functional property in embedded real-Time systems (ERTS). ERTS increasingly require higher levels of performance that can only be sensibly provided by deploying high-performance hardware, which however ...
  • Multi-level unified caches for probabilistically time analysable real-time systems 

    Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (IEEEXPLORE, 2013)
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    Caches are key resources in high-end processor architectures to increase performance. In fact, most high-performance processors come equipped with a multi-level cache hierarchy. In terms of guaranteed performance, however, ...
  • On reducing register pressure and energy in multiple-banked register files 

    Abella Ferrer, Jaume; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2003)
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    The storage for speculative values in superscalar processors is one of the main sources of complexity and power dissipation. We present a novel technique to reduce register requirements as well as their dynamic and static ...
  • On the convergence of mainstream and mission-critical markets 

    Girbal, Sylvain; Moreto Planas, Miquel; Grasset, Arnaud; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Yehia, Sami (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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    The computing market has been dominated during the last two decades by the well-known convergence of the highperformance computing market and the mobile market. In this paper we witness a new type of convergence between ...
  • On-line failure detection and confinement in caches 

    Abella Ferrer, Jaume; Chaparro, Pedro; Vera Rivera, Francisco Javier; Carretero Casado, Javier Sebastián; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2008)
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    Technology scaling leads to burn-in phase out and increasing post-silicon test complexity, which increases in-the-field error rate due to both latent defects and actual errors. As a consequence, there is an increasing need ...
  • Online error detection and correction of erratic bits in register files 

    Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; Carretero Casado, Javier Sebastián; Chaparro Valero, Pedro Alonso; González Colás, Antonio María (2009-06)
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    Aggressive voltage scaling needed for low power in each new process generation causes large deviations in the threshold voltage of minimally sized devices of the 6T SRAM cell. Gate oxide scaling can cause large transient ...
  • Optimizing program locality through CMEs and GAs 

    Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; González Colás, Antonio María; Llosa Espuny, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2003)
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    Caches have become increasingly important with the widening gap between main memory and processor speeds. Small and fast cache memories are designed to bridge this discrepancy. However, they are only effective when programs ...
  • Penelope: The NBTI-aware processor 

    Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society, 2007)
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    Transistors consist of lower number of atoms with every technology generation. Such atoms may be displaced due to the stress caused by high temperature, frequency and current, leading to failures. NBTI (negative bias ...
  • Power efficient data cache designs 

    Abella Ferrer, Jaume; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2003)
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    We investigate some power efficient data cache designs that try to significantly reduce the cache energy consumption, both static and dynamic, with a minimal impact in performance. The basic idea is to combine different ...
  • Power- and complexity-aware issue queue designs 

    Abella Ferrer, Jaume; Canal Corretger, Ramon; González Colás, Antonio María (2003-09)
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    The improved performance of current microprocessors brings with it increasingly complex and power-dissipating issue logic. Recent proposals introduce a range of mechanisms for tackling this problem.
  • Probabilistic timing analysis on conventional cache designs 

    Kosmidis, Leonidas; Curtsinger, Charlie; Quiñones, Eduardo; Abella Ferrer, Jaume; Berger, Emery D.; Cazorla Almeida, Francisco Javier (2013)
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    Probabilistic timing analysis (PTA), a promising alternative to traditional worst-case execution time (WCET) analyses, enables pairing time bounds (named probabilistic WCET or pWCET) with an exceedance probability (e.g., ...
  • Probabilistically time-analyzable complex processors in hard real- time systems 

    Slijepcevic, Mladen; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Barcelona Supercomputing Center, 2015-05-05)
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    Critical Real-Time Embedded Systems (CRTES) feature performance-demanding functionality. High-performance hardware and complex software can provide such functionality, but the use of aggressive technology challenges ...
  • Random Modulo: A new processor cache design for real-time critical systems 

    Hernández, Carles; Abella Ferrer, Jaume; Gianarro, Andrea; Andersson, Jan; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    Cache memories have a huge impact on software's worst-case execution time (WCET). While enabling the seamless use of caches is key to provide the increasing levels of (guaranteed) performance required by automotive software, ...
  • Resilient random modulo cache memories for probabilistically-analyzable real-time systems 

    Trilla, David; Hernández, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    Fault tolerance has often been assessed separately in safety-related real-time systems, which may lead to inefficient solutions. Recently, Measurement-Based Probabilistic Timing Analysis (MBPTA) has been proposed to estimate ...
  • RunPar: An allocation algorithm for automotive applications exploiting runnable parallelism in multicores 

    Panic, Milos; Kehr, Sebastian; Quiñones, Eduardo; Boddecker, Bert; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2014)
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    Automotive applications increasingly rely on AUTOSAR for their design and execution. AUTOSAR applications comprise functions, called runnables, that are grouped into AUTOSAR tasks. Tasks are the unit of scheduling (UoS) ...
  • RVC: A mechanism for time-analyzable real-time processors with faulty caches 

    Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Sazeides, Yanos; Valero Cortés, Mateo (2011)
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    Geometry scaling due to technology evolution as well as Vcc scaling lead to failures in large SRAM arrays such as caches. Faulty bits can be tolerated from the average performance perspective, but make critical realtime ...
  • SAMIE-LSQ: set-associative multiple-instruction entry load/store queue 

    Abella Ferrer, Jaume; González Colás, Antonio María (IEEE Computer Society, 2006)
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    The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processor hotspots. This paper presents a highly ...