Now showing items 17-34 of 34

  • Hardware/software-based diagnosis of load-store queues using expandable activity logs 

    Carretero Casado, Javier Sebastián; Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; Ramírez García, Tanausu; Monchiero, Matteo; González Colás, Antonio María (IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
    Conference report
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    The increasing device count and design complexity are posing significant challenges to post-silicon validation. Bug diagnosis is the most difficult step during post-silicon validation. Limited reproducibility and low testing ...
  • Implementing end-to-end register data-flow continuous self-test 

    Carretero Casado, Javier Sebastián; Chaparro, Pedro; Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; González Colás, Antonio María (2011-08-01)
    Article
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    While Moore's Law predicts the ability of semiconductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in that law. One concern is the verification effort ...
  • Low Vccmin fault-tolerant cache with highly predictable performance 

    Abella Ferrer, Jaume; Carretero Casado, Javier Sebastián; Chaparro Valero, Pedro Alonso; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Press. Institute of Electrical and Electronics Engineers, 2009)
    Conference report
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    Transistors per area unit double in every new technology node. However, the electric field density and power demand grow if Vcc is not scaled. Therefore, Vcc must be scaled in pace with new technology nodes to prevent ...
  • Measurement-based probabilistic timing analysis for multi-path programs 

    Cucu Grosjean, Liliana; Santinelli, Luca; Houston, Michael; Lo, Code; Vardanega, Tulio; Kosmidis, Leonidas; Abella Ferrer, Jaume; Mezzetti, Enrico; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier (2012)
    Conference report
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    The rigorous application of static timing analysis requires a large and costly amount of detail knowledge on the hardware and software components of the system. Probabilistic Timing Analysis has potential for reducing the ...
  • Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case study 

    Wartel, Franck; Kosmidis, Leonidas; Lo, Code; Triquet, Benoit; Quiñones Moreno, Eduardo; Abella Ferrer, Jaume; Gogonel, Adriana; Baldovin, Andrea; Mezzetti, Enrico; Cucu Grosjean, Liliana; Vardanega, Tulio; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2013)
    Conference report
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    Probabilistic Timing Analysis (PTA) in general and its measurement-based variant called MBPTA in particular can mitigate some of the problems that impair current worst-case execution time (WCET) analysis techniques. MBPTA ...
  • Multi-level unified caches for probabilistically time analysable real-time systems 

    Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier (IEEEXPLORE, 2013)
    Conference report
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    Caches are key resources in high-end processor architectures to increase performance. In fact, most high-performance processors come equipped with a multi-level cache hierarchy. In terms of guaranteed performance, however, ...
  • On the convergence of mainstream and mission-critical markets 

    Girbal, Sylvain; Moreto Planas, Miquel; Grasset, Arnaud; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Cazorla, Francisco J.; Yehia, Sami (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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    The computing market has been dominated during the last two decades by the well-known convergence of the highperformance computing market and the mobile market. In this paper we witness a new type of convergence between ...
  • Online error detection and correction of erratic bits in register files 

    Vera, Xavier; Abella Ferrer, Jaume; Carretero Casado, Javier Sebastián; Chaparro Valero, Pedro Alonso; González Colás, Antonio María (2009-06)
    Conference report
    Open Access
    Aggressive voltage scaling needed for low power in each new process generation causes large deviations in the threshold voltage of minimally sized devices of the 6T SRAM cell. Gate oxide scaling can cause large transient ...
  • Probabilistic timing analysis on conventional cache designs 

    Kosmidis, Leonidas; Curtsinger, Charlie; Quiñones Moreno, Eduardo; Abella Ferrer, Jaume; Berger, Emery D.; Cazorla Almeida, Francisco Javier (2013)
    Conference report
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    Probabilistic timing analysis (PTA), a promising alternative to traditional worst-case execution time (WCET) analyses, enables pairing time bounds (named probabilistic WCET or pWCET) with an exceedance probability (e.g., ...
  • Probabilistically time-analyzable complex processors in hard real- time systems 

    Slijepcevic, Mladen; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Barcelona Supercomputing Center, 2015-05-05)
    Conference report
    Open Access
    Critical Real-Time Embedded Systems (CRTES) feature performance-demanding functionality. High-performance hardware and complex software can provide such functionality, but the use of aggressive technology challenges ...
  • RVC: A mechanism for time-analyzable real-time processors with faulty caches 

    Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Sazeides, Yanos; Valero Cortés, Mateo (2011)
    Conference report
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    Geometry scaling due to technology evolution as well as Vcc scaling lead to failures in large SRAM arrays such as caches. Faulty bits can be tolerated from the average performance perspective, but make critical realtime ...
  • Selective replication: a lightweight technique for soft errors 

    Vera, Xavier; Abella Ferrer, Jaume; Carretero Casado, Javier Sebastián; González Colás, Antonio María (ACM Press. Association for Computing Machinery, 2009-12)
    Article
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    Soft errors are an important challenge in contemporary microprocessors. Modern processors have caches and large memory arrays protected by parity or error detection and correction codes. However, today’s failure rate is ...
  • Software directed issue queue power reduction 

    Jones, Timothy M.; O’Boyle, Michael F.P.; Abella Ferrer, Jaume; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2005)
    Conference report
    Open Access
    The issue logic of a superscalar processor dissipates a large amount of static and dynamic power. Furthermore, its power density makes it a hot-spot requiring expensive cooling systems and additional packaging. In this ...
  • The next convergence: High-performance and mission-critical markets 

    Girbal, Sylvain; Moreto Planas, Miquel; Grasset, Arnaud; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier; Yehia, Sami (2013)
    Conference report
    Open Access
    The well-known convergence of the high-performance computing and the mobile markets has been a dominating factor in the computing market during the last two decades. In this paper we witness a new type of convergence between ...
  • Time-analysable non-partitioned shared caches for real-time multicore systems 

    Slijepcevic, Mladen; Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2014)
    Conference report
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    Shared caches in multicores challenge Worst-Case Execution Time (WCET) estimation due to inter-task interferences. Hard-ware and software cache partitioning address this issue although they complicate data sharing among ...
  • Variations-aware circuit designs for microprocessors 

    Pons Solé, Marc; Moll Echeto, Francisco de Borja; Abella Ferrer, Jaume (2010)
    Conference lecture
    Open Access
    A new trend that is becoming dominant is to improve layout regularity so that the layouts to be printed are more repetitive and easy to manufacture. Our proposal is to push to the limit layout regularity to minimize ...
  • VCTA: A Via-Configurable Transistor Array regular fabric 

    Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society Publications, 2010)
    Conference report
    Open Access
    Layout regularity is introduced progressively by integrated circuit manufacturers to reduce the increasing systematic process variations in the deep sub-micron era. In this paper we focus on a scenario where layout regularity ...
  • Via-configurable transistor array: a regular design technique to improve ICs yield 

    Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio, Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (2007-09)
    Conference report
    Open Access
    Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That is why regular techniques with different degrees of regularity are emerging as possible solutions. Our ...