Now showing items 7-26 of 34

  • Containing timing-related certification cost in automotive systems deploying complex hardware 

    Kosmidis, Leonidas; Quiñones Moreno, Eduardo; Abella Ferrer, Jaume; Farrall, Glenn; Wartel, Franck; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2014)
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    Measurement-Based Probabilistic Timing Analysis (MBPTA) techniques simplify deriving tight and trustworthy WCET estimates for industrial-size programs running on complex processors. MBPTA poses some requirements on the ...
  • Contention in multicore hardware shared resources: Understanding of the state of the art 

    Fernández, Gabriel; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Rochange, Christine; Vardanega, Tullio; Cazorla Almeida, Francisco Javier (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2014)
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    The real-time systems community has over the years devoted considerable attention to the impact on execution timing that arises from contention on access to hardware shared resources. The relevance of this problem has been ...
  • Control-flow recovery validation using microarchitectural invariants 

    Carretero Casado, Javier Sebastián; Abella Ferrer, Jaume; Vera Gómez, Javier; Chaparro Valero, Pedro Alonso (2011)
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    Processors' design complexity increases with transistors' growing density. At the same time, market competence requires a decreasing time-to-market, and therefore, reduced validation time. Such time reduction imposes new ...
  • Deconstructing bus access control policies for real-time multicores 

    Jalle Ibarra, Javier; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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    Multicores may satisfy the growing performance requirements of critical Real-Time systems which has made industry to consider them for future real-time systems. In a multicore, the bus contention-control policy plays a key ...
  • Design of complex circuits using the via-configurable transistor array regular layout fabric 

    Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society Publications, 2011)
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    Layout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new ...
  • DReAM: Per-task DRAM energy metering in multicore systems 

    Liu, Qixiao; Moreto Planas, Miquel; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (Springer, 2014)
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    Interaction across applications in DRAM memory impacts its energy consumption. This paper makes the case for accurate per-task DRAM energy metering in multicores, which opens new paths to energy/performance optimizations, ...
  • DTM: degraded test mode for fault-aware probabilistic timing analysis 

    Slijepcevic, Mladen; Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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    Existing timing analysis techniques to derive Worst-Case Execution Time (WCET) estimates assume that hardware in the target platform (e.g., the CPU) is fault-free. Given the performance requirements increase in current ...
  • Efficient cache architectures for reliable hybrid voltage operation using EDC codes 

    Maric, Bojan; Abella Ferrer, Jaume; Valero Cortés, Mateo (2013)
    Conference report
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    Semiconductor technology evolution enables the design of sensor-based battery-powered ultra-low-cost chips (e.g., below 1 p) required for new market segments such as body, urban life and environment monitoring. Caches have ...
  • Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study 

    González Colás, Antonio María; Pons Solé, Marc; Barajas Ojeda, Enrique; Mateo Peña, Diego; López González, Juan Miguel; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier (IEEE Computer Society Publications, 2011)
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    Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated ...
  • FOCSI: A new layout regularity metric 

    Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (2009-06-09)
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    Digital CMOS Integrated Circuits (ICs) suffer from serious layout features printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to reduce ...
  • Hardware/software-based diagnosis of load-store queues using expandable activity logs 

    Carretero Casado, Javier Sebastián; Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; Ramírez García, Tanausu; Monchiero, Matteo; González Colás, Antonio María (IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
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    The increasing device count and design complexity are posing significant challenges to post-silicon validation. Bug diagnosis is the most difficult step during post-silicon validation. Limited reproducibility and low testing ...
  • Implementing end-to-end register data-flow continuous self-test 

    Carretero Casado, Javier Sebastián; Chaparro, Pedro; Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; González Colás, Antonio María (2011-08-01)
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    While Moore's Law predicts the ability of semiconductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in that law. One concern is the verification effort ...
  • Low Vccmin fault-tolerant cache with highly predictable performance 

    Abella Ferrer, Jaume; Carretero Casado, Javier Sebastián; Chaparro Valero, Pedro Alonso; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Press. Institute of Electrical and Electronics Engineers, 2009)
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    Transistors per area unit double in every new technology node. However, the electric field density and power demand grow if Vcc is not scaled. Therefore, Vcc must be scaled in pace with new technology nodes to prevent ...
  • Measurement-based probabilistic timing analysis for multi-path programs 

    Cucu Grosjean, Liliana; Santinelli, Luca; Houston, Michael; Lo, Code; Vardanega, Tulio; Kosmidis, Leonidas; Abella Ferrer, Jaume; Mezzetti, Enrico; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier (2012)
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    The rigorous application of static timing analysis requires a large and costly amount of detail knowledge on the hardware and software components of the system. Probabilistic Timing Analysis has potential for reducing the ...
  • Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case study 

    Wartel, Franck; Kosmidis, Leonidas; Lo, Code; Triquet, Benoit; Quiñones Moreno, Eduardo; Abella Ferrer, Jaume; Gogonel, Adriana; Baldovin, Andrea; Mezzetti, Enrico; Cucu Grosjean, Liliana; Vardanega, Tulio; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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    Probabilistic Timing Analysis (PTA) in general and its measurement-based variant called MBPTA in particular can mitigate some of the problems that impair current worst-case execution time (WCET) analysis techniques. MBPTA ...
  • Multi-level unified caches for probabilistically time analysable real-time systems 

    Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier (IEEEXPLORE, 2013)
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    Caches are key resources in high-end processor architectures to increase performance. In fact, most high-performance processors come equipped with a multi-level cache hierarchy. In terms of guaranteed performance, however, ...
  • On the convergence of mainstream and mission-critical markets 

    Girbal, Sylvain; Moreto Planas, Miquel; Grasset, Arnaud; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Cazorla, Francisco J.; Yehia, Sami (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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    The computing market has been dominated during the last two decades by the well-known convergence of the highperformance computing market and the mobile market. In this paper we witness a new type of convergence between ...
  • Online error detection and correction of erratic bits in register files 

    Vera, Xavier; Abella Ferrer, Jaume; Carretero Casado, Javier Sebastián; Chaparro Valero, Pedro Alonso; González Colás, Antonio María (2009-06)
    Conference report
    Open Access
    Aggressive voltage scaling needed for low power in each new process generation causes large deviations in the threshold voltage of minimally sized devices of the 6T SRAM cell. Gate oxide scaling can cause large transient ...
  • Probabilistic timing analysis on conventional cache designs 

    Kosmidis, Leonidas; Curtsinger, Charlie; Quiñones Moreno, Eduardo; Abella Ferrer, Jaume; Berger, Emery D.; Cazorla Almeida, Francisco Javier (2013)
    Conference report
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    Probabilistic timing analysis (PTA), a promising alternative to traditional worst-case execution time (WCET) analyses, enables pairing time bounds (named probabilistic WCET or pWCET) with an exceedance probability (e.g., ...
  • Probabilistically time-analyzable complex processors in hard real- time systems 

    Slijepcevic, Mladen; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Barcelona Supercomputing Center, 2015-05-05)
    Conference report
    Open Access
    Critical Real-Time Embedded Systems (CRTES) feature performance-demanding functionality. High-performance hardware and complex software can provide such functionality, but the use of aggressive technology challenges ...