Now showing items 1-13 of 13

  • Adaptive fault-tolerant architecture for unreliable device technologies 

    Aymerich Capdevila, Nivard; Cotofana, Sorin; Rubio Sola, Jose Antonio (IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
    Conference report
    Restricted access - publisher's policy
    This paper introduces an efficient adaptive redundant architecture, which makes use of the averaging cell (AVG) principle in order to improve the reliability of nanoscale circuits and systems. We define an adaptive averaging ...
  • Adaptive fault-tolerant architecture for unreliable technologies with heterogeneous variability 

    Aymerich Capdevila, Nivard; Cotofana, Sorin; Rubio Sola, Jose Antonio (2012-07)
    Article
    Restricted access - publisher's policy
    This paper introduces an efficient adaptive redundant architecture, which makes use of the averaging cell (AVG) principle in order to improve the reliability of nanoscale circuits and systems. We propose an adaptive structure ...
  • Controlled degradation stochastic resonance in adaptive averaging cell-based architectures 

    Aymerich Capdevila, Nivard; Cotofana, Sorin; Rubio Sola, Jose Antonio (2013-11)
    Article
    Restricted access - publisher's policy
    In this paper, we first analyze the degradation stochastic resonance (DSR) effect in the context of adaptive averaging (AD-AVG) architectures. The AD-AVG is the adaptive version of the well-known AVG architecture . It is ...
  • Extending the fundamental error bounds for asymmetric error reliable computation 

    Aymerich Capdevila, Nivard; Rubio Sola, Jose Antonio (IEEE Industrial Electronics Society, 2013)
    Conference report
    Restricted access - publisher's policy
    Future computing systems based on new emerging nanotechnologies will have to rely on very high failure rate devices. Therefore, the study of fault-tolerant architectures is of great interest today. One of the most challenging ...
  • Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy 

    Aymerich Capdevila, Nivard; Rubio Sola, Jose Antonio (2012-07)
    Article
    Restricted access - publisher's policy
    One of the main objectives of the data computing and memory industry is to keep and ever accelerate the increase of component density reached in nowadays integrated circuits in future technologies based on ultimate CMOS ...
  • Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy 

    Aymerich Capdevila, Nivard; Rubio Sola, Jose Antonio (2010)
    Conference report
    Open Access
    One of the main objectives of the data computing and memory industry is to keep and ever accelerate the increase of component density reached in nowadays integrated circuits in future technologies based on ultimate CMOS ...
  • Impact of finfet and III-V/Ge technology on logic and memory cell behavior 

    Amat Bertran, Esteve; Calomarde Palomino, Antonio; García Almudéver, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2013-11-20)
    Article
    Restricted access - publisher's policy
    In this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability scenarios ...
  • Impact of positive bias temperature instability (PBTI) 

    Aymerich Capdevila, Nivard; Ganapathy, Shrikanth; Rubio Sola, Jose Antonio; Canal Corretger, Ramon; González Colás, Antonio María (2011)
    Conference report
    Restricted access - publisher's policy
    Memory circuits are playing a key role in complex multicore systems with both data and instructions storage and mailbox communication functions. There is a general concern that conventional SRAM cell based on the 6T structure ...
  • Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm 

    Amat Bertran, Esteve; García Almudéver, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2012)
    Conference report
    Open Access
    3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability. In this contribution, we have shown that 22nm 3T1D memory cells present significant ...
  • Reliability and performance tunable architecture: the partially asynchronous R-Fold modular redundancy (pA-RMR) 

    Aymerich Capdevila, Nivard; Rubio Sola, Jose Antonio (2014-04-02)
    Article
    Restricted access - publisher's policy
    The R-fold modular redundancy (RMR) is a widely known fault-tolerant architecture based on hardware redundancy. It improves the system reliability by replicating the basic computing element and combining all the results ...
  • Study on the optimal distribution of redundancy effort in cross-layer reliable architectures 

    Aymerich Capdevila, Nivard; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2013)
    Conference report
    Restricted access - publisher's policy
    This paper presents a comprehensive approach to the smart application of redundancy techniques in multiple-layer hierarchical systems. Computing systems today are rapidly evolving into increasingly complex structures with ...
  • Systematic and random variability analysis of two different 6T-SRAM layout topologies 

    Amat Bertran, Esteve; Amatlle, E.; Gómez González, Sergio; Aymerich Capdevila, Nivard; García Almudéver, Carmen; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2013-09)
    Article
    Open Access
  • Variability-aware architectures based on hardware redundancy for nanoscale reliable computation 

    Aymerich Capdevila, Nivard (Universitat Politècnica de Catalunya, 2013-12-16)
    Doctoral thesis