Now showing items 1-11 of 11

  • Design of complex circuits using the via-configurable transistor array regular layout fabric 

    Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society Publications, 2011)
    Conference report
    Restricted access - publisher's policy
    Layout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new ...
  • Energy macro-model for on chip interconnection buses 

    Mendoza Vázquez, Raymundo; Pons Solé, Marc; Moll Echeto, Francisco de Borja; Figueras, Joan (2006-06)
    External research report
    Open Access
    This report presents a fast method of evaluating the power consumption of a bus. Given an on-chip bus driver-interconnection-receiver design of N parallel lines,the objective is to develop its energy consumption macro-model. ...
  • Error probability in synchronous digital circuits due to power supply noise 

    Martorell Cid, Ferran; Pons Solé, Marc; Rubio, Antonio; Moll Echeto, Francisco de Borja (2007-09)
    Conference report
    Open Access
    This paper presents a probabilistic approach to model the problem of power supply voltage fluctuations. Error probability calculations are shown for some 90-nm technology digital circuits. The analysis here considered ...
  • Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study 

    González Colás, Antonio María; Pons Solé, Marc; Barajas Ojeda, Enrique; Mateo Peña, Diego; López González, Juan Miguel; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier (IEEE Computer Society Publications, 2011)
    Conference lecture
    Restricted access - publisher's policy
    Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated ...
  • FOCSI: A new layout regularity metric 

    Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (2009-06-09)
    External research report
    Open Access
    Digital CMOS Integrated Circuits (ICs) suffer from serious layout features printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to reduce ...
  • Layout regularity for design and manufacturability 

    Pons Solé, Marc (Universitat Politècnica de Catalunya, 2012-10-02)
    Doctoral thesis
  • Power supply noise and logic error probability 

    Andrade Miceli, Dennis Michael; Martorell Cid, Ferran; Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio, Antonio (2007-08)
    Conference report
    Open Access
    Voltage fluctuations caused by parasitic impedances in the power supply rails of modern ICs are a major concern in nowadays ICs. The voltage fluctuations are spread out to the diverse nodes of the internal sections causing ...
  • Variations-aware circuit designs for microprocessors 

    Pons Solé, Marc (Centre de Publicacions del Campus Nord SCCL (CPET), 2009)
    Conference lecture
    Open Access
  • Variations-aware circuit designs for microprocessors 

    Pons Solé, Marc; Moll Echeto, Francisco de Borja; Abella Ferrer, Jaume (2010)
    Conference lecture
    Open Access
    A new trend that is becoming dominant is to improve layout regularity so that the layouts to be printed are more repetitive and easy to manufacture. Our proposal is to push to the limit layout regularity to minimize ...
  • VCTA: A Via-Configurable Transistor Array regular fabric 

    Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society Publications, 2010)
    Conference report
    Open Access
    Layout regularity is introduced progressively by integrated circuit manufacturers to reduce the increasing systematic process variations in the deep sub-micron era. In this paper we focus on a scenario where layout regularity ...
  • Via-configurable transistor array: a regular design technique to improve ICs yield 

    Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio, Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (2007-09)
    Conference report
    Open Access
    Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That is why regular techniques with different degrees of regularity are emerging as possible solutions. Our ...