Ara es mostren els items 1-20 de 29

  • A case for acoustic wave detectors for soft-errors 

    Upasani, Gaurang; Vera Rivera, Francisco Javier; González Colás, Antonio María (2016-01-01)
    Article
    Accés restringit per política de l'editorial
    The continuing decrease in dimensions and operating voltage of transistors has increased their sensitivity against radiation phenomena, making soft errors an important challenge in future microprocessors. New techniques ...
  • An efficient solver for Cache Miss Equations 

    Bermudo, Nerina; Vera Rivera, Francisco Javier; González Colás, Antonio María; Llosa Espuny, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2000)
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    Cache Miss Equations (CME) (S. Ghosh et al., 1997) is a method that accurately describes the cache behavior by means of polyhedra. Even though the computation cost of generating CME is a linear function of the number of ...
  • Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery 

    Upasani, Gaurang; Vera Rivera, Francisco Javier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2014)
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    The trend of downsizing transistors and operating voltage scaling has made the processor chip more sensitive against radiation phenomena making soft errors an important challenge. New reliability techniques for handling ...
  • Design of complex circuits using the via-configurable transistor array regular layout fabric 

    Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society Publications, 2011)
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    Layout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new ...
  • Empowering a helper cluster through data-width aware instruction selection policies 

    Unsal, Osman Sabri; Ergin, Oguz; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society, 2006)
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    Narrow values that can be represented by less number of bits than the full machine width occur very frequently in programs. On the other hand, clustering mechanisms enable cost- and performance-effective scaling of processor ...
  • Exploiting narrow values for soft error tolerance 

    Ergin, Oguz; Unsal, Osman Sabri; Vera Rivera, Francisco Javier; González Colás, Antonio María (2006-07)
    Article
    Accés obert
    Soft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. ...
  • Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study 

    González Colás, Antonio María; Pons Solé, Marc; Barajas Ojeda, Enrique; Mateo Peña, Diego; López González, Juan Miguel; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier (IEEE Computer Society Publications, 2011)
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    Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated ...
  • FOCSI: A new layout regularity metric 

    Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (2009-06-09)
    Report de recerca
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    Digital CMOS Integrated Circuits (ICs) suffer from serious layout features printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to reduce ...
  • Framework for economical error recovery in embedded cores 

    Upasani, Gaurang; Vera Rivera, Francisco Javier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2014)
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    The vulnerability of the current and future processors towards transient errors caused by particle strikes is expected to increase rapidly because of exponential growth rate of on-chip transistors, the lower voltages and ...
  • Fuse: A technique to anticipate failures due to degradation in ALUs 

    Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; Unsal, Osman Sabri; Ergin, Oguz; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2007)
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    This paper proposes the fuse, a technique to anticipate failures due to degradation in any ALU (arithmetic logic unit), and particularly in an adder. The fuse consists of a replica of the weakest transistor in the adder ...
  • Hardware/software-based diagnosis of load-store queues using expandable activity logs 

    Carretero Casado, Javier Sebastián; Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; Ramírez García, Tanausu; Monchiero, Matteo; González Colás, Antonio María (IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
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    The increasing device count and design complexity are posing significant challenges to post-silicon validation. Bug diagnosis is the most difficult step during post-silicon validation. Limited reproducibility and low testing ...
  • High-Performance low-vcc in-order core 

    Abella Ferrer, Jaume; Chaparro, Pedro; Vera Rivera, Francisco Javier; Carretero Casado, Javier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2010)
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    Power density grows in new technology nodes, thus requiring Vcc to scale especially in mobile platforms where energy is critical. This paper presents a novel approach to decrease Vcc while keeping operating frequency high. ...
  • Impact of parameter variations on circuits and microarchitecture 

    Unsal, Osman Sabri; Tschanz, James W.; Bowman, Keith; De, Vivek; Vera Rivera, Francisco Javier; González Colás, Antonio María; Ergin, Oguz (2006-12)
    Article
    Accés obert
    Parameter variations, which are increasing along with advances in process technologies, affect both timing and power. Variability must be considered at both the circuit and microarchitectural design levels to keep pace ...
  • Implementing end-to-end register data-flow continuous self-test 

    Carretero Casado, Javier Sebastián; Chaparro, Pedro; Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; González Colás, Antonio María (2011-08-01)
    Article
    Accés restringit per política de l'editorial
    While Moore's Law predicts the ability of semiconductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in that law. One concern is the verification effort ...
  • Low Vccmin fault-tolerant cache with highly predictable performance 

    Abella Ferrer, Jaume; Carretero Casado, Javier Sebastián; Chaparro Valero, Pedro Alonso; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Press. Institute of Electrical and Electronics Engineers, 2009)
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    Transistors per area unit double in every new technology node. However, the electric field density and power demand grow if Vcc is not scaled. Therefore, Vcc must be scaled in pace with new technology nodes to prevent ...
  • MT-SBST: self-test optimization in multithreaded multicore architectures 

    Foutris, Nikos; Psarakis, M.; Gizopoulos, Dimitris; Apostolakis, A.; Vera Rivera, Francisco Javier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2010)
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    Instruction-based or software-based self-testing (SBST) is a scalable functional testing paradigm that has gained increasing acceptance in testing of single-threaded uniprocessors. Recent computer architecture trends towards ...
  • Near-optimal loop tiling by means of cache miss equations and genetic algorithms 

    Abella Ferrer, Jaume; González Colás, Antonio María; Llosa Espuny, José Francisco; Vera Rivera, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2002)
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    The effectiveness of the memory hierarchy is critical for the performance of current processors. The performance of the memory hierarchy can be improved by means of program transformations such as loop tiling, which is a ...
  • On-line failure detection and confinement in caches 

    Abella Ferrer, Jaume; Chaparro, Pedro; Vera Rivera, Francisco Javier; Carretero Casado, Javier Sebastián; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2008)
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    Technology scaling leads to burn-in phase out and increasing post-silicon test complexity, which increases in-the-field error rate due to both latent defects and actual errors. As a consequence, there is an increasing need ...
  • Online error detection and correction of erratic bits in register files 

    Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; Carretero Casado, Javier Sebastián; Chaparro Valero, Pedro Alonso; González Colás, Antonio María (2009-06)
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    Aggressive voltage scaling needed for low power in each new process generation causes large deviations in the threshold voltage of minimally sized devices of the 6T SRAM cell. Gate oxide scaling can cause large transient ...
  • Optimizing program locality through CMEs and GAs 

    Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; González Colás, Antonio María; Llosa Espuny, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2003)
    Text en actes de congrés
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    Caches have become increasingly important with the widening gap between main memory and processor speeds. Small and fast cache memories are designed to bridge this discrepancy. However, they are only effective when programs ...