Now showing items 1-20 of 41

  • A case study of hybrid dataflow and shared-memory programming models: Dependency-based parallel game engine 

    Gajinov, Vladimir; Eric, Igor; Stojanovic, Saa; Milutinovic, Veljko; Unsal, Osman Sabri; Ayguadé Parra, Eduard; Cristal Kestelman, Adrián (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
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    Recently proposed hybrid dataflow and shared memory programming models combine these two underlying models in order to support a wider range of problems naturally. The effectiveness of such hybrid models for parallel ...
  • Advanced pattern based memory controller for FPGA based HPC applications 

    Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
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    The ever-increasing complexity of high-performance computing applications limits performance due to memory constraints in FPGAs. To address this issue, we propose the Advanced Pattern based Memory Controller (APMC), which ...
  • AMMC: advance multi-core memory controller 

    Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference lecture
    Open Access
    In this work, we propose an efficient scheduler and intelligent memory manager known as AMMC (Advanced Multi-Core Memory Controller), which proficiently handles data movement and computational tasks. The proposed AMMC ...
  • Atomic quake: using transactional memory in an interactive mulitplayer game Server 

    Zyulkyarov, Ferad; Gajinov, Vladimir; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Harris, Tim; Valero Cortés, Mateo (2009)
    Conference report
    Open Access
    Transactional Memory (TM) is being studied widely as a new technique for synchronizing concurrent accesses to shared memory data structures for use in multi-core systems. Much of the initial work on TM has been evaluated ...
  • Circuit design of a novel adaptable and reliable L1 data cache 

    Seyedi, Azam; Yalcin, Gulay; Unsal, Osman Sabri; Cristal Kestelman, Adrián (2013)
    Conference report
    Open Access
    This paper proposes a novel adaptable and reliable L1 data cache design (Adapcache) with the unique capability of automatically adapting itself for different supply voltage levels and providing the highest reliability. ...
  • DaSH: a benchmark suite for hybrid dataflow and shared memory programming models: with comparative evaluation of three hybrid dataflow models 

    Gajinov, Vladimir; Stipic, Srdjan; Eric, Igor; Unsal, Osman Sabri; Ayguadé Parra, Eduard; Cristal Kestelman, Adrián (Association for Computing Machinery (ACM), 2014)
    Conference report
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    The current trend in development of parallel programming models is to combine different well established models into a single programming model in order to support efficient implementation of a wide range of real world ...
  • DeTrans: Deterministic and parallel execution of transactions 

    Smiljkovic, Vesna; Stipic, Srdjan; Fetzer, Christof; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
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    Deterministic execution of a multithreaded application guarantees the same output as long as the application runs with the same input parameters. Determinism helps a programmer to test and debug an application and to provide ...
  • DLP acceleration on general purpose cores 

    Duric, Milovan; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Barcelona Supercomputing Center, 2015-05-05)
    Conference report
    Open Access
    High-performance and power-efficient multimedia computing drives the design of modern and increasingly utilized mobile devices. State-of-the-art low power processors already utilize chip multiprocessors (CMP) that add ...
  • Dynamic transaction coalescing 

    Stipic, Srdjan; Karakostas, Vasileios; Smiljkovic, Vesna; Gajinov, Vladimir; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2014)
    Conference report
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    Prior work in Software Transactional Memory has identified high overheads related to starting and committing transactions that may degrade the application performance. To amortize these overheads, transaction coalescing ...
  • Dynamic-vector execution on a general purpose EDGE chip multiprocessor 

    Duric, Milovan; Palomar Pérez, Óscar; Smith, Aaron; Stanic, Milan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo; Burger, Doug; Veidenbaum, Alexander V (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
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    This paper proposes a cost-effective technique that morphs the available cores of a low power chip multiprocessor (CMP) into an accelerator for data parallel (DLP) workloads. Instead of adding a special-purpose vector ...
  • Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi 

    Stanic, Milan; Palomar Pérez, Óscar; Ratkovic, Ivan; Duric, Milovan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
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    Graph500 is a data intensive application for high performance computing and it is an increasingly important workload because graphs are a core part of most analytic applications. So far there is no work that examines if ...
  • EVX: vector execution on low power EDGE cores 

    Duric, Milovan; Palomar Pérez, Óscar; Smith, Aaron; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo; Burger, Doug (European Interactive Digital Advertising Alliance (EDAA), 2014)
    Conference report
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    In this paper, we present a vector execution model that provides the advantages of vector processors on low power, general purpose cores, with limited additional hardware. While accelerating data-level parallel (DLP) ...
  • FaulTM: Error detection and recovery using hardware transactional memory 

    Yalcin, Gulay; Unsal, Osman Sabri; Cristal Kestelman, Adrián (2013)
    Conference report
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    Reliability is an essential concern for processor designers due to increasing transient and permanent fault rates. Executing instruction streams redundantly in chip multi processors (CMP) provides high reliability since ...
  • From plasma to beefarm: Design experience of an FPGA-based multicore prototype 

    Sonmez, N.; Arcas, O.; Sayilar, G.; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Hur, Ibrahim; Singh, S.; Valero Cortés, Mateo (Springer Verlag, 2011)
    Conference report
    Open Access
    In this paper, we take a MIPS-based open-source uniprocessor soft core, Plasma, and extend it to obtain the Beefarm infrastructure for FPGA-based multiprocessor emulation, a popular research topic of the last few years ...
  • Hardware scheduling algorithms for asymmetric single-ISA CMPs 

    Markovic, Nikola; Nemirovsky, Daniel; Unsal, Osman Sabri; Valero Cortés, Mateo; Cristal Kestelman, Adrián (Barcelona Supercomputing Center, 2015-05-05)
    Conference report
    Open Access
    As thread level parallelism in applications has continued to expand, so has research in chip multi-core processors. Since more and more applications become multi-threaded we expect to find a growing number of threads ...
  • Hybrid transactional memory with pessimistic concurrency control 

    Vallejo, Enrique; Sanyal, Sutirtha; Harris, Tim; Vallejo, Fernando; Beivide, Ramón; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2011-06)
    Article
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    Transactional Memory (TM) intends to simplify the design and implementation of the shared-memory data structures used in parallel software. Many Software TM systems are based on writer-locks to protect the data being ...
  • Improving the energy efficiency of hardware-assisted watchpoint systems 

    Karakostas, Vasileios; Tomić, Saša; Unsal, Osman Sabri; Nemirovsky, Mario; Cristal Kestelman, Adrián (2013)
    Conference report
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    Hardware-assisted watchpoint systems enhance the execution of numerous dynamic software techniques, such as memory protection, module isolation, deterministic execution, and data race detection. In this paper, we show ...
  • Integrating dataflow abstractions into the shared memory model 

    Gajinov, Vladimir; Stipic, Srdjan; Unsal, Osman Sabri; Harris, Tim; Ayguadé Parra, Eduard; Cristal Kestelman, Adrián (2012)
    Conference report
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    In this paper we present Atomic Dataflow model (ADF), a new task-based parallel programming model for C/C++ which integrates dataflow abstractions into the shared memory programming model. The ADF model provides pragma ...
  • Integrating dataflow abstractions into transactional memory 

    Gajinov, Vladimir; Milovanovic, Milos; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (2011)
    Conference report
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    Many concurrent programs require some form of conditional synchronization to coordinate the execution of different program tasks. Programming these algorithms using transactional memory (TM) often results in a high ...
  • MAPC: memory access pattern based controller 

    Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
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    Traditionally, system designers have attempted to improve system performance by scheduling the processing cores and by exploring different memory system configurations and there is comparatively less work done scheduling ...