Ara es mostren els items 1-20 de 71

  • A highly scalable parallel implementation of H.264 

    Azevedo, Arnaldo; Juurlink, Ben; Meenderinck, Cor; Terechko, Andrei; Hoogerbrugge, Jan; Álvarez Mesa, Mauricio; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2011)
    Article
    Accés obert
    Developing parallel applications that can harness and efficiently use future many-core architectures is the key challenge for scalable computing systems. We contribute to this challenge by presenting a parallel implementation ...
  • A module-based cell processor simulator 

    Cabarcas Jaramillo, Felipe; Rico Carro, Alejandro; Rodenas, David; Martorell Bofill, Xavier; Ramírez Bellido, Alejandro; Ayguadé Parra, Eduard (European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC), 2006)
    Comunicació de congrés
    Accés obert
    An interesting design alternative to replication-based chip multiprocessors is to create heterogeneous chip multiprocessors composed of several different cores, with one or more of them running the operating system and ...
  • A performance perspective on energy efficient HPC links 

    Saravanan, Karthikeyan P.; Carpenter, Paul; Ramírez Bellido, Alejandro (Association for Computing Machinery (ACM), 2014)
    Comunicació de congrés
    Accés obert
    Energy costs are an increasing part of the total cost of ownership of HPC systems. As HPC systems become increasingly energy proportional in an effort to reduce energy costs, interconnect links stand out for their inefficiency. ...
  • A polymorphic register file for matrix operations 

    Ciobanu, Catalin; Kuzmanov, Georgi; Gaydadjiev, Georgi; Ramírez Bellido, Alejandro (IEEE Computer Society Publications, 2010)
    Text en actes de congrés
    Accés obert
    Previous vector architectures divided the available register file space in a fixed number of registers of equal sizes and shapes. We propose a register file organization which allows dynamic creation of a variable number ...
  • A streaming machine description and programming model 

    Carpenter, Paul; Ródenas Picó, David; Martorell Bofill, Xavier; Ramírez Bellido, Alejandro; Ayguadé Parra, Eduard (2007-07)
    Article
    Accés restringit per política de l'editorial
    In this paper we present the initial development of a streaming environment based on a programming model and machine description. The stream programming model consists of an extension to the C language and it’s translation ...
  • ACOTES project: Advanced compiler technologies for embedded streaming 

    Duranton, M.; Munk, H.; Ayguadé Parra, Eduard; Bastoul, C.; Carpenter, Paul; Chamski, Z.; Cohen, A.; Cornero, M.; Dumont, P.; Pop, S.; Pop, A.; Ornstein, A.; Nuzman, D.; Miranda, C.; Martorell Bofill, Xavier; Lindwer, M.; Ladelsky, R.; Ferrer, Roger; Fellahi, M.; Pouchet, L. N; Zaks, A.; Shvadron, U.; Trifunovic, K.; Rohou, E.; Rosen, I.; Ramírez Bellido, Alejandro; Ródenas, D. (2011-04)
    Article
    Accés obert
    Streaming applications are built of data-driven, computational components, consuming and producing unbounded data streams. Streaming oriented systems have become dominant in a wide range of domains, including embedded ...
  • Archexplorer for automatic design space exploration 

    Desmet, V.; Girbal, Sylvain; Ramírez Bellido, Alejandro; Temam, Olivier; Vega, Augusto (2010-09-09)
    Article
    Accés obert
    Growing architectural complexity and stringent time-to-market constraints suggest the need to move architecture design beyond parametric exploration to structural exploration. ArchExplorer is a Web-based permanent and open ...
  • Author retrospective for "Software trace cache" 

    Ramírez Bellido, Alejandro; Falcón Samper, Ayose Jesus; Santana Jaria, Oliverio J.; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2014)
    Text en actes de congrés
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    In superscalar processors, capable of issuing and executing multiple instructions per cycle, fetch performance represents an upper bound to the overall processor performance. Unless there is some form of instruction re-use ...
  • Better branch prediction through prophet/critic hybrids 

    Falcón Samper, Ayose Jesús; Stark, Jared; Ramírez Bellido, Alejandro; Lai, Konrad; Valero Cortés, Mateo (2005-01)
    Article
    Accés obert
    The prophet/critic hybrid conditional branch predictor has two component predictors. The prophet uses a branch's history to predict its direction. We call this prediction and the ones for branches following it the branch ...
  • Branch classification to control instruction fetch in simultaneous multithreaded architectures 

    Knijnenburg, Peter M.W.; Ramírez Bellido, Alejandro; Latorre Salinas, Fernando; Larriba Pey, Josep; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2002)
    Text en actes de congrés
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    In simultaneous multithreaded architectures many separate threads are running concurrently, sharing processor resources, thereby realizing a high utilization rate of the available hardware. However, this also implies that ...
  • Buffer sizing for self-timed stream programs on heterogeneous distributed memory multiprocessors 

    Carpenter, Paul; Ramírez Bellido, Alejandro; Ayguadé Parra, Eduard (Springer Verlag, 2010)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Stream programming is a promising way to expose concurrency to the compiler. A stream program is built from kernels that communicate only via point-to-point streams. The stream compiler statically allocates these kernels ...
  • CellSim: a validated modular heterogeneous multiprocessor simulator 

    Cabarcas Jaramillo, Felipe; Rico Carro, Alejandro; Ródenas Picó, David; Martorell Bofill, Xavier; Ramírez Bellido, Alejandro; Ayguadé Parra, Eduard (Thomson Editores Spain, 2007)
    Text en actes de congrés
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    As the number of transistors on a chip continues increasing the power consumption has become the most important constraint in processors design. Therefore, to increase performance, computer architects have decided to use ...
  • Code layout optimizations for transaction processing workloads 

    Ramírez Bellido, Alejandro; Barroso, Luiz A; Gharachorloo, Kourosh; Cohn, Robert; Larriba Pey, Josep; Lowney, P. Geoffrey; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2001)
    Text en actes de congrés
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    Commercial applications such as databases and Web servers constitute the most important market segment for high-performance servers. Among these applications, on-line transaction processing (OLTP) workloads provide a ...
  • COMalaWEB: plataforma basada en noves tecnologies aplicades a la docència 

    Fernández Rubio, Juan Antonio; Fernández Prades, Carlos; Ramírez Bellido, Alejandro; Cabrera Beán, Margarita Asuncion; Pomar Berry, Christian (2005-02)
    Text en actes de congrés
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    Les possibilitats que ens ofereixen les noves tecnologies de la informació aplicades a l’àmbit de la docència és un tema encara no prou ben explotat. Aquest projecte pretén investigar aquests conceptes mitjançant la creació ...
  • Comparing last-level cache designs for CMP architectures 

    Vega, Augusto; Rico Carro, Alejandro; Cabarcas, Felipe; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2010)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    The emergence of hardware accelerators, such as graphics processing units (GPUs), has challenged the interaction between processing elements (PEs) and main memory. In architectures like the Cell/B.E. or GPUs, the PEs ...
  • Data placement in HPC architectures with heterogeneous off-chip memory 

    Pavlovic, Milan; Puzovic, Nikola; Ramírez Bellido, Alejandro (Institute of Electrical and Electronics Engineers (IEEE), 2013)
    Text en actes de congrés
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    The performance of HPC applications is often bounded by the underlying memory system's performance. The trend of increasing the number of cores on a chip imposes even higher memory bandwidth and capacity requirements. The ...
  • Dcache Warn: an I-fetch policy to increase SMT efficiency 

    Cazorla Almeida, Francisco Javier; Ramírez Bellido, Alejandro; Valero Cortés, Mateo; Fernandez Garcia, Enrique (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Text en actes de congrés
    Accés obert
    Simultaneous multithreading (SMT) processors increase performance by executing instructions from multiple threads simultaneously. These threads share the processor's resources, but also compete for them. In this environment, ...
  • DIA: A complexity-effective decoding architecture 

    Santana Jaria, Oliverio J.; Falcón Samper, Ayose Jesus; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2009-04)
    Article
    Accés obert
    Fast instruction decoding is a true challenge for the design of CISC microprocessors implementing variable-length instructions. A well-known solution to overcome this problem is caching decoded instructions in a hardware ...
  • Dynamically controlled resource allocation in SMT processors 

    Cazorla Almeida, Francisco Javier; Ramírez Bellido, Alejandro; Valero Cortés, Mateo; Fernandez Prieto, Enrique (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Text en actes de congrés
    Accés obert
    SMT processors increase performance by executing instructions from several threads simultaneously. These threads use the resources of the processor better by sharing them but, at the same time, threads are competing for ...
  • Effective instruction prefetching via fetch prestaging 

    Falcón Samper, Ayose Jesús; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2005)
    Text en actes de congrés
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    As technological process shrinks and clock rate increases, instruction caches can no longer be accessed in one cycle. Alternatives are implementing smaller caches (with higher miss rate) or large caches with a pipelined ...