Ara es mostren els items 1-20 de 33

    • 8T SRAM Cell with Open Defects under Voltage and Timing Variations 

      Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pàmies, Joan; Castillo Muñoz, Raul (2011)
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    • A forming-free ReRAM cell with low operating voltage 

      Yang, Binbin; Xu, Nuo; Li, Cheng; Huang, Chenglong; Ma, Desheng; Liu, Jiahao; Arumi Delgado, Daniel; Fang, Liang (2020-11-25)
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      The unwanted electro-forming process is unavoidable for the practical application of most resistive random access memory (ReRAM) devices, which is always being one of the obstacles for the massive commercialization of this ...
    • Backside polishing detector: a new protection against backside attacks 

      Manich Bou, Salvador; Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Mujal Colell, Jordi; Hernández García, David (2015)
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      Secure chips are in permanent risk of attacks. Physical attacks usually start removing part of the package and accessing the dice by different means: laser shots, electrical or electromagnetic probes, etc. Doing this ...
    • BIST Architecture to Detect Defects in TSVs During Pre-Bond Testing 

      Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pàmies, Joan (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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      Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs). The detection of defective TSVs in the earliest process step is of major concern. Hence, testing TSVs is usually done ...
    • Defective Behaviour of an 8T SRAM Cell with Open Defects 

      Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Manich Bou, Salvador; Figueras Pàmies, Joan; Di Carlo, Stefano; Prinetto, Paolo; Scionti, Alberto (2010)
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    • Design and validation of a platform for electromagnetic fault injection 

      Balasch, Josep; Arumi Delgado, Daniel; Manich Bou, Salvador (Institute of Electrical and Electronics Engineers (IEEE), 2018)
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      Security is acknowledged as one of the main challenges in the design and deployment of embedded circuits. Devices need to operate on-the-field safely and correctly, even when at physical reach of potential adversaries. One ...
    • Diagnosis of full open defects in interconnect lines with fan-out 

      Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pàmies, Joan; Eichenberger, Stefan; Hora, C.; Kruseman, Bram (IEEE Press. Institute of Electrical and Electronics Engineers, 2010-05-24)
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      The development of accurate diagnosis methodologies is important to solve process problems and achieve fast yield improvement. As open defects are common in CMOS technologies, accurate diagnosis of open defects becomes ...
    • Diagnosis of full open defects in interconnecting lines 

      Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pàmies, Joan; Eichenberger, Stefan; Hora, Camelia; Kruseman, Bram; Lousberg, M.; Majhi, A.K. (IEEE, 2007-05-31)
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      A proposal for enhancing the diagnosis of full open defects in interconnecting lines of CMOS circuits is presented. The defective line is first classified as fully opened by means of a logic-based diagnosis tool (Faloc). ...
    • Enhanced serial RRAM cell for unpredictable bit generation 

      Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Gómez-Pau, Álvaro; Manich Bou, Salvador; Bargalló González, Mireia; Campabadal, Francesca (2021-05)
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      In this letter, the serial configuration of two RRAMs is used as a basic cell to generate an unpredictable bit. The basis of the operation considers starting from the Low Resistive State (LRS) in both devices (initialization ...
    • ETS 2022 ORGANIZING COMMITTEE 

      Manich Bou, Salvador; Rodríguez Montañés, Rosa; Bernardi, Paolo; Tille, Daniel; Mir, Salvador; Bosio, Alberto; Arumi Delgado, Daniel; Gómez Pau, Álvaro; Cassano, Luca; Jiao, Hailong; Miclea, Liviu; Sanchez, Ernesto; Savino, Alessandro; Canal Corretger, Ramon; Eggersglüß, Stephan; Fransi, Sergi; Taouil, Mottaqiallah; Calomarde Palomino, Antonio; Weiner, Michael; Michael, Maria K.; Sonza Reorda, Matteo; Larsson, Erik; Vatajelu, Elena-Ioana; Stratigopoulos, Haralampos-G.; Parisi Baradad, Vicenç; Jiao, Hailong; Huang, Junlin; Li, Huawei; Chillarige, Sameer; Kameyama, Shuichi; Carro, Luigi; Su, Fei; Nicolici, Nicola; Huang, Shi-Yu (2022-05)
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    • Gate leakage impact on full open defects in interconnect lines 

      Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pàmies, Joan; Eichenberger, Stefan; Hora, Camelia; Kruseman, Bram (2011-06)
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      An Interconnect full open defect breaks the connection between the driver and the gate terminals of downstream transistors, generating a floating line. The behavior of floating lines is known to depend on several factors, ...
    • Impact of gate tunnelling leakage on CMOS circuits with full open defects 

      Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pàmies, Joan; Eichenberger, S.; Hora, Camelia; Kruseman, B. (Institution of Electrical Engineers, 2007-10)
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      Interconnecting lines with full open defects become floating lines. In nanometric CMOS technologies, gate tunnelling leakage currents impact the behaviour of these lines, which cannot be considered electrically isolated ...
    • Impact of laser attacks on the switching behavior of RRAM devices 

      Arumi Delgado, Daniel; Manich Bou, Salvador; Gómez Pau, Álvaro; Rodríguez Montañés, Rosa; Montilla, Víctor; Hernández, David; Bargalló González, Mireia; Campabadal, Francesca (2020-01-20)
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      The ubiquitous use of critical and private data in electronic format requires reliable and secure embedded systems for IoT devices. In this context, RRAMs (Resistive Random Access Memories) arises as a promising alternative ...
    • Localization and electrical characterization of interconnect open defects 

      Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pàmies, Joan; Beverloo, Willem; Vries, Dirk K. de; Eichenberger, Stefan; Volf, Paul A. J. (2010-02)
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      A technique for extracting the electrical and topological parameters of open defects in process monitor lines is presented. The procedure is based on frequency-domain measurements performed at both end points of the ...
    • Low Cost AES Protection Against DPA Using Rolling Codes 

      Albiol Perarnau, Pau; Manich Bou, Salvador; Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Gómez-Pau, Álvaro (Curran Associates, Inc., 2021)
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      Many block cipher algorithms like AES are known to be weak against differential power analysis attacks (DPA) if the executing unit presents certain levels of information leakage, which is a common problem in microprocessors. ...
    • On the fitting and improvement of RRAM stanford-based model parameters using TiN/Ti/HfO2/W experimental data 

      Mahboubi, Vahab; Arumi Delgado, Daniel; Gómez Pau, Álvaro; Rodríguez Montañés, Rosa; Manich Bou, Salvador (Institute of Electrical and Electronics Engineers (IEEE), 2022)
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      The use of Resistive Random Access Memory (RRAM) devices is becoming pervasive in many applications. In particular, security based primitives can exploit their variability and non-volatility for generating cells for ...
    • Post-Bond test of through-silicon vias with open defects 

      Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pàmies, Joan (2014)
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      Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs) and are susceptible to undergo defects at different stages: during their own fabrication, the bonding stage or during ...
    • Postbond test of through-silicon vias with resistive open defects 

      Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pàmies, Joan (2019-07-17)
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      Through-silicon vias (TSVs) technology has attracted industry interest as a way to achieve high bandwidth, and short interconnect delays in nanometer three-dimensional integrated circuits (3-D ICs). However, TSVs are ...
    • Prebond testing of weak defects in TSVs 

      Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pàmies, Joan (2015-08-07)
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      Accés restringit per política de l'editorial
      Through-silicon vias (TSVs) are critical elements in 3-D integrated circuits susceptible to defects during fabrication and lifetime. It is desirable to detect defective TSVs in the early steps of the fabrication process ...
    • Programming techniques of resistive random-access memory devices for neuromorphic computing 

      Machado Panadés, Pau; Manich Bou, Salvador; Gómez Pau, Álvaro; Rodríguez Montañés, Rosa; Bargalló González, Mireia; Campabadal, Francesca; Arumi Delgado, Daniel (2023-11-27)
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      Neuromorphic computing offers a promising solution to overcome the von Neumann bottleneck, where the separation between the memory and the processor poses increasing limitations of latency and power consumption. For this ...