Exploració per altres contribucions "Cristal Kestelman, Adrián"
Ara es mostren els items 1-20 de 30
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A multithreading RISC-V implementation for Lagarto Architecture
(Universitat Politècnica de Catalunya, 2020-04)
Projecte Final de Màster Oficial
Accés obertThe development of computer architecture standards for many years was mainly delegated to a few groups of companies that define most of the popular Instructions Set Architectures (ISAs). While the Information Technologies ... -
Adaptable register file organization for vector processors
(Universitat Politècnica de Catalunya, 2022-04-04)
Tesi
Accés obertToday there are two main vector processors design trends. On the one hand, we have vector processors designed for long vectors lengths such as the SX-Aurora TSUBASA which implements vector lengths of 256 elements (16384-bits). ... -
Advanced analytics through FPGA based query processing and deep reinforcement learning
(Universitat Politècnica de Catalunya, 2019-02-12)
Tesi
Accés obertToday, vast streams of structured and unstructured data have been incorporated in databases, and analytical processes are applied to discover patterns, correlations, trends and other useful relationships that help to take ... -
Affordable kilo-instruction processors
(Universitat Politècnica de Catalunya, 2008-12-09)
Tesi
Accés obertDiversos motius expliquen l'estancament en el que es troba el desenvolupament del processador tradicional dissenyat per maximitzar el rendiment d'un únic fil d'execució. Per una banda, técniques agressives com la supersegmentacó ... -
Aggressive undervolting of FPGAs : power & reliability trade-offs
(Universitat Politècnica de Catalunya, 2018-11-19)
Tesi
Accés obertIn this work, we evaluate aggressive undervolting, i.e., voltage underscaling below the nominal level to reduce the energy consumption of Field Programmable Gate Arrays (FPGAs). Usually, voltage guardbands are added by ... -
Atomic dataflow model
(Universitat Politècnica de Catalunya, 2014-11-20)
Tesi
Accés obertWith the recent switch in the design of general purpose processors from frequency scaling of a single processor core towards increasing the number of processor cores, parallel programming became important not only for ... -
Beehive: an FPGA-based multiprocessor architecture
(Universitat Politècnica de Catalunya, 2009-09-23)
Projecte Final de Màster Oficial
Accés obertIn recent years, to accomplish with the Moore's law hardware and software designers are tending progressively to focus their efforts on exploiting instruction-level parallelism. Software simulation has been essential for ... -
Circuit designs for increasing reliability and reducing energy
(Universitat Politècnica de Catalunya, 2016-02-02)
Tesi
Accés obertComputing technology has witnessed an inimitable progress in the last decades which is the result of CMOS technology scaling commensurate with Moore's law. Transistor feature sizes have shrunk to half at each generation, ... -
Design and implementation of a Multimedia Extension for a RISC Processor
(Universitat Politècnica de Catalunya, 2015-07-02)
Projecte Final de Màster Oficial
Accés obertDesign and implementation of a Multimedia Extension for a RISC Processor in a FPGA -
Design and implementation of an out of order execution engine of floating point arithmetic operations
(Universitat Politècnica de Catalunya, 2016-02-04)
Projecte Final de Màster Oficial
Accés obert
Realitzat a/amb: Instituto Politécnico Nacional. Centro de Investigación en ComputaciónIn this thesis, work is undertaken towards the design in hardware description languages and implementation in FPGA of an out of order execution engine of floating point arithmetic operations. This thesis work, is part of ... -
Design of a Load / Store Queue with Out-of-Order Execution
(Universitat Politècnica de Catalunya, 2016-01)
Projecte Final de Màster Oficial
Accés restringit per acord de confidencialitat -
Designs for increasing reliability while reducing energy and increasing lifetime
(Universitat Politècnica de Catalunya, 2014-12-12)
Tesi
Accés obertIn the last decades, the computing technology experienced tremendous developments. For instance, transistors' feature size shrank to half at every two years as consistently from the first time Moore stated his law. ... -
Efficient hardware acceleration of deep neural networks via arithmetic complexity reduction
(Universitat Politècnica de Catalunya, 2023-10-26)
Tesi
Accés obert(English) Over the past decade, significant progresses in the field of artificial intelligence have led to remarkable advancements in a wide range of technologies. Deep learning, a subfield of machine learning centered ... -
Enhancing the efficiency and practicality of software transactional memory on massively multithreaded systems
(Universitat Politècnica de Catalunya, 2013-03-22)
Tesi
Accés obertChip Multithreading (CMT) processors promise to deliver higher performance by running more than one stream of instructions in parallel. To exploit CMT's capabilities, programmers have to parallelize their applications, ... -
Extending the applicability of deterministic multithreading
(Universitat Politècnica de Catalunya, 2016-01-12)
Tesi
Accés obertWith the increased number of cores on a single processor chip, an application can achieve good performance if it splits the execution into multiple threads that run on multiple cores at the same time. To synchronize threads, ... -
From FPGA to ASIC: A RISC-V processor experience
(Universitat Politècnica de Catalunya, 2019-10-25)
Projecte Final de Màster Oficial
Accés obert
Realitzat a/amb: Instituto Politécnico Nacional. Centro de Investigación en ComputaciónThis work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC. -
Hardware thread scheduling algorithms for single-ISA asymmetric CMPs
(Universitat Politècnica de Catalunya, 2015-12-22)
Tesi
Accés obertThrough the past several decades, based on the Moore's law, the semiconductor industry was doubling the number of transistors on the single chip roughly every eighteen months. For a long time this continuous increase in ... -
Improving heterogeneous system efficiency : architecture, scheduling, and machine learning
(Universitat Politècnica de Catalunya, 2017-10-30)
Tesi
Accés obertComputer architects are beginning to embrace heterogeneous systems as an effective method to utilize increases in transistor densities for executing a diverse range of workloads under varying performance and energy ... -
Improving the performance and energy-efficiency of virtual memory
(Universitat Politècnica de Catalunya, 2016-04-18)
Tesi
Accés obertVirtual memory improves programmer productivity, enhances process security, and increases memory utilization. However, virtual memory requires an address translation from the virtual to the physical address space on every ... -
Low Energy DRAM Controller for Computer Systems
(Universitat Politècnica de Catalunya, 2019-07-04)
Projecte Final de Màster Oficial
Accés obertIn this work, we leverage an open source simulation framework to evaluate different memory scheduling algorithms and we provide an architectural design of a memory controller, which is implemented in Verilog and tested on ...