Exploració per autor "Llosa Espuny, José Francisco"
Ara es mostren els items 1-20 de 33
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A case for resource-conscious out-of-order processors
(2003-12)
Article
Accés obertModern out-of-order processors tolerate long-latency memory operations by supporting a large number of in-flight instructions. This is achieved in part through proper sizing of critical resources, such as register files ... -
A low cost split-issue technique to improve performance of SMT clustered VLIW processors
(2010)
Text en actes de congrés
Accés obertAbstract—Very Long Instruction Word (VLIW) processors are a popular choice in embedded domain due to their hardware simplicity, low cost and low power consumption. Simultaneous MultiThreading (SMT) is a popular technique for ... -
An efficient solver for Cache Miss Equations
(Institute of Electrical and Electronics Engineers (IEEE), 2000)
Text en actes de congrés
Accés obertCache Miss Equations (CME) (S. Ghosh et al., 1997) is a method that accurately describes the cache behavior by means of polyhedra. Even though the computation cost of generating CME is a linear function of the number of ... -
Aprendizaje activo basado en problemas
(Universitat Jaume I. Escola Superior de Tecnologia i Ciències Experimentals, 2013-07-10)
Text en actes de congrés
Accés obertDurante años, los autores del presente trabajo hemos practicado diversos métodos para fomentar el aprendizaje activo de los estudiantes a partir de la resolución de problemas, tanto en clase como fuera de ella. Los ... -
Aprenentatge actiu basat en problemes
(Universitat Politècnica de Catalunya. Institut de Ciències de l'Educació, 2014-04-24)
Text en actes de congrés
Accés obertDurant anys, els autors del present treball hem practicat diversos mètodes per fomentar l'aprenentatge actiu dels estudiants a partir de la resolució de problemes, tant a la classe com fora. Els últims quatre cursos hem ... -
Cost-conscious strategies to increase performance of numerical programs on agressive VLIW architectures
(2001-10)
Article
Accés obertLoops are the main time-consuming part of numerical applications. The performance of the loops is limited either by the resources offered by the architecture or by recurrences in the computation. To execute more operations ... -
El impacto de eliminar el examen final
(2016-09)
Article
Accés obertDesde hace algún tiempo se publican en JENUI artículos donde se argumenta sobre la conveniencia de eliminar el examen final como forma de fomentar el trabajo del estudiante durante todo el curso. Convencidos de lo apropiado ... -
Evaluación formativa con feedback rápido usando mandos interactivos
(Universidade de Santiago de Compostela. Escola Técnica Superior d'Enxeñaría, 2010-07-07)
Comunicació de congrés
Accés obertNumerosos estudios han demostrado que el uso del feedback como herramienta docente resulta beneficioso para el aprendizaje. Para que este feedback sea útil debe ser rápido, es decir, llegar al alumno poco después de ... -
Heuristics for register-constrained software pipelining
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
Text en actes de congrés
Accés obertSoftware Pipelining is a loop scheduling technique that extracts parallelism from loops by overlapping the execution of several consecutive iterations. There has been a significant effort to produce throughput-optimal ... -
Hierarchical clustered register file organization for VLIW processors
(IEEE Computer Society, 2003)
Text en actes de congrés
Accés obertTechnology projections indicate that wire delays will become one of the biggest constraints in future microprocessor designs. To avoid long wire delays and therefore long cycle times, processor cores must be partitioned ... -
Hybrid multithreading for VLIW processors
(2009-10)
Text en actes de congrés
Accés obertSeveral multithreading techniques have been proposed to reduce resource underutilization in Very Long Instruction Word (VLIW) processors. Simultaneous MultiThreading (SMT) is a popular technique that improves processor ... -
Hypernode reduction modulo scheduling
(Institute of Electrical and Electronics Engineers (IEEE), 1995)
Text en actes de congrés
Accés obertSoftware pipelining is a loop scheduling technique that extracts parallelism from loops by overlapping the execution of several consecutive iterations. Most prior scheduling research has focused on achieving minimum execution ... -
Impact on performance of fused multiply-add units in aggressive VLIW architectures
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Text en actes de congrés
Accés obertLoops are the main time consuming part of programs based on floating point computations. The performance of the loops is limited either by recurrences in the computation or by the resources offered by the architecture. ... -
El Impacto de eliminar el examen final
(Universidad de Almería, 2016-07-06)
Comunicació de congrés
Accés obertDesde hace algún tiempo se publican en JENUI artículos donde se argumenta sobre la conveniencia de eliminar el examen final como forma de fomentar el trabajo del estudiante durante todo el curso. Convencidos de lo apropiado ... -
Incorporació de sistemes de resposta interactiva a la docència presencial
(Universitat Politècnica de Catalunya. Institut de Ciències de l'Educació, 2010-02-11)
Comunicació de congrés / Text en actes de congrés
Accés obertAquest projecte, de Suport a la Docència, consisteix en la incorporació d’uns comandaments amb botons del 0 al 9 a les classes per tal de donar suport als professors a les seves classes i, d’aquesta manera, avaluar els ... -
Lifetime-sensitive modulo scheduling in a production environment
(2001-03)
Article
Accés obertThis paper presents a novel software pipelining approach, which is called Swing Modulo Scheduling (SMS). It generates schedules that are near optimal in terms of initiation interval, register requirements, and stage count. ... -
Lightning talks of EduHPC 2022
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertThe lightning talks at EduHPC provide an opportunity to share early results and insights on parallel and distributed computing (PDC) education and training efforts. The four lightning talks at EduHPC 2022 cover a range of ... -
Mirs: modulo scheduling with integrated register spilling
(2003-01)
Article
Accés restringit per política de l'editorialThe overlapping of loop iterations in software pipelining techniques imposes high register requirements. The schedule for a loop is valid if it requires at most the number of registers available in the target architecture. ... -
Modulo scheduling with integrated register spilling for clustered VLIW architectures
(Institute of Electrical and Electronics Engineers (IEEE), 2001)
Text en actes de congrés
Accés obertClustering is a technique to decentralize the design of future wide issue VLIW cores and enable them to meet the technology constraints in terms of cycle time, area and power dissipation. In a clustered design, registers ... -
Modulo scheduling with reduced register pressure
(1998-06)
Article
Accés obertSoftware pipelining is a scheduling technique that is used by some product compilers in order to expose more instruction level parallelism out of innermost loops. Module scheduling refers to a class of algorithms for ...
