Ara es mostren els items 1-20 de 93

  • 1-D memristor networks as ternary storage cells 

    Vourkas, Ioannis; Abusleme, Angel; Sirakoulis, Georgios; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    Due to its inherent analog nature, the memristor can store information in a continuous form, being thus well-suited for compact multi-bit memory cell technology. In this context, threshold-type switching devices show great ...
  • A comparative variability analysis for CMOS and CNFET 6T SRAM cells 

    García Almudéver, Carmen; Rubio Sola, Jose Antonio (2011)
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    Statistical device variability may be a limiting factor for further miniaturizing nodes in silicon bulk CMOS technology. On the other hand, in novel technologies such as Carbon Nanotubes Field Effect Transistors (CNFETs), ...
  • A comprehensive compensation technique for process variations and environmental fluctuations in digital integrated circuits 

    Andrade Miceli, Dennis Michael; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio (IEEE Press. Institute of Electrical and Electronics Engineers, 2010)
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    Abstract—Process variability and environmental fluctuations deeply affect the digital circuits performance in many different ways, one of them, the data processing time which may cause error on synchronous digital circuits ...
  • A crosstalk latch circuit design 

    Rubio Sola, Jose Antonio; Pons Nin, Joan; Anglada, Raimon (Institute of Electrical and Electronics Engineers (IEEE), 1990)
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    A D-latch sequential circuit design is presented that exhibits an elevated degree of tolerance to common and differential mode noise in the clock lines. The circuit tolerates noise voltages in the clock signals in the range ...
  • A digital memristor emulator for FPGA-based artificial neural networks 

    Vourkas, Ioanis; Abusleme, A.; Ntinas, V.; Sirakoulis, Georgios Ch.; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    FPGAs are reconfigurable electronic platforms, well-suited to implement complex artificial neural networks (ANNs). To this end, the compact hardware (HW) implementation of artificial synapses is an important step to obtain ...
  • A new probabilistic design methodology of nanoscale digital circuits 

    García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
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    The continuing trends of device scaling and increase in complexity towards terascale system on chip level of integration are putting growing difficulties into several areas of design. The intrinsic variability problem is ...
  • A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance 

    Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Enrico; González Colás, Antonio María; Rubio Sola, Jose Antonio (IEEE Computer Society Publications, 2012)
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    In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition ...
  • A shapeshifting evolvable hardware mechanism based on reconfigurable memFETs crossbar architecture 

    Martín Martínez, Javier; García Almudéver, Carmen; Crespo Yepes, Albert; Rodríguez Martínez, Rosana; Nafría Maqueda, Montserrat; Rubio Sola, Jose Antonio (2014-05-05)
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  • A single event transient hardening circuit design technique based on strengthening 

    Calomarde Palomino, Antonio; Amat Bertran, Esteve; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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    In a near future of high-density and low-power technologies, the study of soft errors will not only be relevant for memory systems and latches of logic circuits, but also for the combinational parts of logic circuits which ...
  • Adaptive fault-tolerant architecture for unreliable device technologies 

    Aymerich, Nivard; Cotofana, Sorin; Rubio Sola, Jose Antonio (CRC Press, Taylor and Francis Group, 2013-06-03)
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    Nanoelectronic Device Applications Handbook gives a comprehensive snapshot of the state of the art in nanodevices for nanoelectronics applications. Combining breadth and depth, the book includes 68 chapters on topics that ...
  • Adaptive fault-tolerant architecture for unreliable device technologies 

    Aymerich Capdevila, Nivard; Cotofana, Sorin; Rubio Sola, Jose Antonio (IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
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    This paper introduces an efficient adaptive redundant architecture, which makes use of the averaging cell (AVG) principle in order to improve the reliability of nanoscale circuits and systems. We define an adaptive averaging ...
  • Adaptive fault-tolerant architecture for unreliable technologies with heterogeneous variability 

    Aymerich Capdevila, Nivard; Cotofana, Sorin; Rubio Sola, Jose Antonio (2012-07)
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    This paper introduces an efficient adaptive redundant architecture, which makes use of the averaging cell (AVG) principle in order to improve the reliability of nanoscale circuits and systems. We propose an adaptive structure ...
  • Adaptive proactive reconfiguration: a technique for process variability and aging aware SRAM cache design 

    Pouyan, Peyman; Amat Bertran, Esteve; Rubio Sola, Jose Antonio (2014)
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    Nanoscale circuits are subject to a wide range of new limiting phenomena making essential to investigate new design strategies at the circuit and architecture level to improve its performance and reliability. Proactive ...
  • Advanced failure detection techniques in deep submicron CMOS integrated circuits 

    Rubio Sola, Jose Antonio; Altet Sanahujes, Josep; Mateo Peña, Diego (Pergamon Press, 2009)
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    The test of present integrated circuits exhibits many confining aspects, among them the adequate selection of the observable variables, the use of combined testing approaches, an each time more restricted controllability ...
  • An on-line test strategy and analysis for a 1T1R crossbar memory 

    Escudero, Manel; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Vourkas, Ioannis (Institute of Electrical and Electronics Engineers (IEEE), 2017)
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    Memristors are emerging devices known by their nonvolability, compatibility with CMOS processes and high density in circuits density in circuits mostly owing to the crossbar nanoarchitecture. One of their most notable ...
  • Analysis and modelling of parasitic substrate coupling in CMOS circuits 

    Aragonès Cervera, Xavier; Moll Echeto, Francisco de Borja; Roca Adrover, Miquel; Rubio Sola, Jose Antonio (1995-10)
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    Analysis of the substrate coupling in integrated circuits is done taking into account technology and layout parameters for different types and location of transistors using a device-level simulator. The noise coupling ...
  • Analysis of delay mismatching of digital circuits caused by common environmental fluctuations 

    Andrade Miceli, Dennis Michael; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio; Cotofana, Sorin (IEEE, 2011)
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    Environmental conditions are changing all the time along the chip as a consequence of its own activity, provoking deviations on propagation time in digital circuits. In future technologies, the increment of devices sensitivity ...
  • Análisis del retardo en enlaces con protocolos ARQ y control de flujo: aplicación a una red estrella 

    Rubio Sola, Jose Antonio; Figueras Pàmies, Joan (Marcombo, 1983)
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    El objetivo de este trabajo se enmarca en el desarrollo de herramientas de cuantificación de los tiempos de retardo en redes de computadores. El análisis se ha centrado en la evaluación del tiempo medio de retardo en el ...
  • Asynchronous pulse logic cell for threshold logic and Boolean networks 

    Lambie, J; Moll Echeto, Francisco de Borja; González Jiménez, José Luis; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2005)
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    In this article, a fully digital CMOS circuit for asynchronous pulse cells is presented. The proposed circuit has a high noise tolerance and no static power consumption. Furthermore it has a high functional programmability. ...
  • Carbon nanotube growth process-related variablity in CNFET's 

    García Almudéver, Carmen; Rubio Sola, Jose Antonio (IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
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    In silicon bulk CMOS technology the variability of the device parameters is a key drawback that may be a limiting factor for further miniaturizing nodes. Novel nanoscale beyond- CMOS devices are being studied such as carbon ...