Exploració per altres contribucions "Valero Cortés, Mateo"
Ara es mostren els items 1-20 de 39
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Adaptive and application dependant runtime guided hardware reconfiguration for the IBM POWER7
(Universitat Politècnica de Catalunya, 2014-09-04)
Projecte Final de Màster Oficial
Accés obertThe aim of this project is to develop adaptive resource management systems for the im- provement of the power-performance metrics associated with the current and future IBM POWER-series microprocessors. -
Affordable kilo-instruction processors
(Universitat Politècnica de Catalunya, 2008-12-09)
Tesi
Accés obertDiversos motius expliquen l'estancament en el que es troba el desenvolupament del processador tradicional dissenyat per maximitzar el rendiment d'un únic fil d'execució. Per una banda, técniques agressives com la supersegmentacó ... -
Analysis and architectural support for parallel stateful packet processing
(Universitat Politècnica de Catalunya, 2008-07-09)
Tesi
Accés obertThe evolution of network services is closely related to the network technology trend. Originally network nodes forwarded packets from a source to a destination in the network by executing lightweight packet processing, or ... -
Analysis and simulation of emergent architectures for internet of things
(Universitat Politècnica de Catalunya, 2018-02-01)
Tesi
Accés obertThe Internet of Things (IoT) promises a plethora of new services and applications supported by a wide range of devices that includes sensors and actuators. To reach its potential IoT must break down the silos that limit ... -
Castell: a heterogeneous cmp architecture scalable to hundreds of processors
(Universitat Politècnica de Catalunya, 2011-09-19)
Tesi
Accés obertTechnology improvements and power constrains have taken multicore architectures to dominate microprocessor designs over uniprocessors. At the same time, accelerator based architectures have shown that heterogeneous ... -
Computación difusa
(Universitat Politècnica de Catalunya, 2007-05-16)
Tesi
Accés obertEsta tesis se enmarca en el ámbito de las técnicas de mejora de la eficiencia de ejecución (disminución del consumo y aumento de la velocidad) en el diseño de procesadores orientados a la ejecución de aplicaciones multimedia. ... -
CPU accounting in multi-threaded processors
(Universitat Politècnica de Catalunya, 2014-05-29)
Tesi
Accés obertIn recent years, multi-threaded processors have become more and more popular in industry in order to increase the system aggregated performance and per-application performance, overcoming the limitations imposed by the ... -
Design of energy-efficient vector units for in-order cores
(Universitat Politècnica de Catalunya, 2017-01-31)
Tesi
Accés obertIn the last 15 years, power dissipation and energy consumption have become crucial design concerns for almost all computer systems. Technology feature size scaling leads to higher power density and therefore to complex and ... -
Evaluating techniques for parallelization tuning in MPI, OmpSs and MPI/OmpSs
(Universitat Politècnica de Catalunya, 2013-07-26)
Tesi
Accés obertParallel programming is used to partition a computational problem among multiple processing units and to define how they interact (communicate and synchronize) in order to guarantee the correct result. The performance that ... -
Exploring average-case and probabilistic worst-case performance of time randomised caches and their associated overheads
(Universitat Politècnica de Catalunya, 2016-01)
Projecte Final de Màster Oficial
Accés obertIn this work we focus on the analysis of performance in the context of Probabilistic Timing Analysis (PTA) from different angles. First, we model and evaluate average performance of time-randomised caches used in the context ... -
Exploring coordinated software and hardware support for hardware resource allocation
(Universitat Politècnica de Catalunya, 2009-09-04)
Tesi
Accés obertMultithreaded processors are now common in the industry as they offer high performance at a low cost. Traditionally, in such processors, the assignation of hardware resources between the multiple threads is done implicitly, ... -
Exploring Scalability Techniques of OmpSs
(Universitat Politècnica de Catalunya, 2014-06-27)
Projecte/Treball Final de Carrera
Accés restringit per acord de confidencialitat -
Hardware thread scheduling algorithms for single-ISA asymmetric CMPs
(Universitat Politècnica de Catalunya, 2015-12-22)
Tesi
Accés obertThrough the past several decades, based on the Moore's law, the semiconductor industry was doubling the number of transistors on the single chip roughly every eighteen months. For a long time this continuous increase in ... -
Heterogeneity-awareness in multithreaded multicore processors
(Universitat Politècnica de Catalunya, 2009-07-07)
Tesi
Accés obertDuring the last decades, Computer Architecture has experienced a great series of revolutionary changes. The increasing transistor count on a single chip has led to some of the main milestones in the field, from the release ... -
High performance instruction fetch using software and hardware co-design
(Universitat Politècnica de Catalunya, 2002-07-12)
Tesi
Accés obertEn los últimos años, el diseño de procesadores de altas prestaciones ha progresado a lo largo de dos corrientes de investigación: incrementar la profundidad del pipeline para permitir mayores frecuencias de reloj, y ensanchar ... -
Improving cache Behavior in CMP architectures throug cache partitioning techniques
(Universitat Politècnica de Catalunya, 2010-03-19)
Tesi
Accés obertThe evolution of microprocessor design in the last few decades has changed significantly, moving from simple inorder single core architectures to superscalar and vector architectures in order to extract the maximum available ... -
Improving heterogeneous system efficiency : architecture, scheduling, and machine learning
(Universitat Politècnica de Catalunya, 2017-10-30)
Tesi
Accés obertComputer architects are beginning to embrace heterogeneous systems as an effective method to utilize increases in transistor densities for executing a diverse range of workloads under varying performance and energy ... -
Improving the efficiency of multicore systems through software and hardware cooperation
(Universitat Politècnica de Catalunya, 2016-10-20)
Tesi
Accés obertIncreasing processors' clock frequency has traditionally been one of the largest drivers of performance improvements for computing systems. In the first half of the 2000s, however, it became clear that continuing to increase ... -
Modelling Contention in Multicore Hardware Resources during Early Design Stages of Real-Time Systems
(Universitat Politècnica de Catalunya, 2016-07)
Projecte Final de Màster Oficial
Accés obertThis thesis presents a modelling approach for the timing behavior of real-time embedded systems in early design phases. The model focuses on multicore processors and it predicts the contention tasks suffer in the access ... -
Novel vector architectures for data management
(Universitat Politècnica de Catalunya, 2015-07-08)
Tesi
Accés obertAs the rate of annual data generation grows exponentially, there is a demand to manage, query and summarise vast amounts of information quickly. In the past, frequency scaling was relied upon to push application throughput. ...
