Ara es mostren els items 1-20 de 212

  • A case for resource-conscious out-of-order processors 

    Cristal Kestelman, Adrián; Martínez, José F; Llosa Espuny, José Francisco; Valero Cortés, Mateo (2003-12)
    Article
    Accés obert
    Modern out-of-order processors tolerate long-latency memory operations by supporting a large number of in-flight instructions. This is achieved in part through proper sizing of critical resources, such as register files ...
  • A discrete optimization problem in local networks and data alignment 

    Fiol Mora, Miquel Àngel; Andrés Yebra, José Luis; Alegre de Miguel, Ignacio; Valero Cortés, Mateo (1987-06)
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    Accés restringit per política de l'editorial
    This paper presents the solution of the following optimization problem that appears in the design of double-loop structures for local networks and also in data memory, allocation and data alignment in SIMD processors. Consider ...
  • A DRAM/SRAM memory scheme for fast packet buffers 

    García Vidal, Jorge; March, Maribel; Cerdà Alabern, Llorenç; Corbal San Adrián, Jesús; Valero Cortés, Mateo (2006-05)
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    Accés obert
    We address the design of high-speed packet buffers for Internet routers. We use a general DRAM/SRAM architecture for which previous proposals can be seen as particular cases. For this architecture, large SRAMs are needed ...
  • A fully parameterizable low power design of vector fused multiply-add using active clock-gating techniques 

    Ratkovic, Ivan; Palomar, Oscar; Stanic, Milan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2016)
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    The need for power-efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a re-tailoring for the mobile market ...
  • A highly scalable parallel implementation of H.264 

    Azevedo, Arnaldo; Juurlink, Ben; Meenderinck, Cor; Terechko, Andrei; Hoogerbrugge, Jan; Álvarez Mesa, Mauricio; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2011)
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    Accés obert
    Developing parallel applications that can harness and efficiently use future many-core architectures is the key challenge for scalable computing systems. We contribute to this challenge by presenting a parallel implementation ...
  • A new pointer-based instruction queue design and its power-performance evaluation 

    Ramírez, Marco A; Cristal Kestelman, Adrián; Veidenbaum, Alexander V; Villa, Luis; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2005)
    Text en actes de congrés
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    Instruction queues consume a significant amount of power in a high-performance processor. The wakeup logic delay is also a critical timing parameter. This paper compares a commonly used CAM-based instruction queue organization ...
  • A systolic algorithm for the fast computation of the connected components of a graph 

    Núñez, Fernando J.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1988)
    Text en actes de congrés
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    The authors consider the description of a systolic algorithm to solve the connected-component problem. It is executed in a ring topology with N processors, requiring O(Nlog N) time without regard to the graph's sparsity. ...
  • A two level load/store queue based on execution locality 

    Pericàs Gleim, Miquel; Cristal Kestelman, Adrián; Cazorla, Francisco; González García, Rubén; Veidenbaum, Alexander V; Jiménez, Daniel A.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
    Text en actes de congrés
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    Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be increasingly limited by the remaining sequential ...
  • Access to streams in multiprocessor systems 

    Valero Cortés, Mateo; Peirón Guardia, Montse; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 1993)
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    When accessing streams in vector multiprocessor machines, degradation in the interconnection network and conflicts in the memory modules are the factors that reduce the efficiency of the system. In this paper, we present ...
  • Access to vectors in multi-module memories 

    Valero Cortés, Mateo; Peiron Guàrdia, Montse; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 1994)
    Text en actes de congrés
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    The poor bandwidth obtained from memory when conflicts arise in the modules or in the interconnection network degrades the performance of computers. Address transformation schemes, such as interleaving, skewing and linear ...
  • ADAM : an efficient data management mechanism for hybrid high and ultra-low voltage operation caches 

    Maric, Bojan; Abella Ferrer, Jaume; Valero Cortés, Mateo (2012)
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    Semiconductor technology evolution enables the design of ultra-low-cost chips (e.g., below 1 USD) required for new market segments such as environment, urban life and body monitoring, etc. Recently, hybrid-operation (high ...
  • Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM Power7 

    Prat Robles, David; Ortega, Cristobal; Casas Guix, Marc; Moretó Planas, Miquel; Valero Cortés, Mateo (2015)
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  • Advanced pattern based memory controller for FPGA based HPC applications 

    Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
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    The ever-increasing complexity of high-performance computing applications limits performance due to memory constraints in FPGAs. To address this issue, we propose the Advanced Pattern based Memory Controller (APMC), which ...
  • Alya: Multiphysics engineering simulation toward exascale 

    Vázquez, Mariano; Houzeaux, Guillaume; Koric, Seid; Artigues, Antoni; Aguado Sierra, Jazmin; Arís Sánchez, Ruth; Mira, Daniel; Calmet, Hadrien; Cucchietti, Fernando; Owen, Herbert; Taha, Ahmed; Dering Burness, Evan; Cela Espín, José M.; Valero Cortés, Mateo (Elsevier, 2016-05)
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    Alya is a multi-physics simulation code developed at Barcelona Supercomputing Center (BSC). From its inception Alya code is designed using advanced High Performance Computing programming techniques to solve coupled problems ...
  • Alya: Multiphysics engineering simulation toward exascale 

    Vázquez, Mariano; Houzeaux, Guillaume; Koric, Seid; Artigues, Antoni; Aguado-Sierra, Jazmin; Arís, Ruth; Mira, Daniel; Calmet, Hadrien; Cucchietti, Fernando; Owen, Herbert; Taha, Ahmed; Burness, Evan D.; Cela, José M.; Valero Cortés, Mateo (Elsevier, 2016-02-01)
    Article
    Accés restringit per política de l'editorial
    Alya is a multi-physics simulation code developed at Barcelona Supercomputing Center (BSC). From its inception Alya code is designed using advanced High Performance Computing programming techniques to solve coupled problems ...
  • AMMC: advance multi-core memory controller 

    Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Comunicació de congrés
    Accés obert
    In this work, we propose an efficient scheduler and intelligent memory manager known as AMMC (Advanced Multi-Core Memory Controller), which proficiently handles data movement and computational tasks. The proposed AMMC ...
  • An abstraction methodology for the evaluation of multi-core multi-threaded architectures 

    Zilan, Ruken; Verdú Mulà, Javier; García Vidal, Jorge; Nemirovsky, Mario; Milito, Rodolfo; Valero Cortés, Mateo (IEEE Computer Society Publications, 2011)
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    As the evolution of multi-core multi-threaded processors continues, the complexity demanded to perform an extensive trade-off analysis, increases proportionally. Cycle-accurate or trace-driven simulators are too slow to ...
  • An analyzable memory controller for hard real-time CMPs 

    Paolieri, Marco; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (2010-02-05)
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    Accés obert
    Multicore processors (CMPs) represent a good solution to provide the performance required by current and future hard real-time systems. However, it is difficult to compute a tight WCET estimation for CMPs due to interferences ...
  • An evaluation of different DLP alternatives for the embedded media domain 

    Salamí San Juan, Esther; Corbal San Adrián, Jesús; Valero Cortés, Mateo; Espasa Sans, Roger (1999)
    Text en actes de congrés
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    The importance of media processing has produced a revolution in the design of embedded processors. In order to face the high computational and technological demands of near future media applications, new embedded processors ...
  • An integrated vector-scalar design on an in-order ARM core 

    Stanic, Milan; Palomar Pérez, Óscar; Hayes, Timothy; Ratkovic, Ivan; Cristal Kestelman, Adrián; Unsal, Osman Sabri; Valero Cortés, Mateo (2017-07)
    Article
    Accés obert
    In the low-end mobile processor market, power, energy, and area budgets are significantly lower than in the server/desktop/laptop/high-end mobile markets. It has been shown that vector processors are a highly energy-efficient ...