Exploració per autor "Amat Bertran, Esteve"

Ara es mostren els items 1-20 de 21

    • A single event transient hardening circuit design technique based on strengthening 

      Calomarde Palomino, Antonio; Amat Bertran, Esteve; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2013)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      In a near future of high-density and low-power technologies, the study of soft errors will not only be relevant for memory systems and latches of logic circuits, but also for the combinational parts of logic circuits which ...

    • Adaptive proactive reconfiguration: a technique for process variability and aging aware SRAM cache design 

      Pouyan, Peyman; Amat Bertran, Esteve; Rubio Sola, Jose Antonio (2014)
      Article
      Accés obert
      Nanoscale circuits are subject to a wide range of new limiting phenomena making essential to investigate new design strategies at the circuit and architecture level to improve its performance and reliability. Proactive ...

    • Design and implementation of an adaptive proactive reconfiguration technique in SRAM caches 

      Pouyan, Peyman; Amat Bertran, Esteve; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2013)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Scaling of device dimensions toward nano-scale regime has made it essential to innovate novel design techniques for improving the circuit robustness. This work proposes an implementation of adaptive proactive reconfiguration ...

    • FinFET and III-V/Ge technology impact on 3T1D cell behavior 

      Amat Bertran, Esteve; Calomarde Palomino, Antonio; Almudever, Carmen G.; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2013)
      Comunicació de congrés
      Accés obert
      In this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability ...

    • Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches 

      Pouyan, Peyman; Amat Bertran, Esteve; Barajas Ojeda, Enrique; Rubio Sola, Jose Antonio (2014)
      Text en actes de congrés
      Accés obert
      This work presents a test and measurement technique to monitor aging and process variation status of SRAM cells as an aging-aware design technique. We have then verified our technique with an implemented chip. The obtained ...

    • Impact of finfet and III-V/Ge technology on logic and memory cell behavior 

      Amat Bertran, Esteve; Calomarde Palomino, Antonio; García Almudéver, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2013-11-20)
      Article
      Accés restringit per política de l'editorial
      In this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability scenarios ...

    • Insights to memristive memory cell from a reliability perspective 

      Pouyan, Peyman; Amat Bertran, Esteve; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2015)
      Text en actes de congrés
      Accés obert
      The scaling roadmap of devices under a more than Moore scenario is resulting in the emergence of new types of devices. Among them, memristors seem to be promising candidates to be suitable for various areas of application ...

    • Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm 

      Amat Bertran, Esteve; García Almudéver, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2012)
      Text en actes de congrés
      Accés obert
      3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability. In this contribution, we have shown that 22nm 3T1D memory cells present significant ...

    • Modem gain-cell memories in advanced technologies 

      Amat Bertran, Esteve; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2018)
      Text en actes de congrés
      Accés obert
      With the advent of the slowdown in DRAM capacitor scaling [1] and the increased reliability problems of traditional 6T SRAM memories [2], industry and academia have looked for alternative memory cells. Among those, gain- ...

    • Proactive reconfiguration, a methodology for extending SRAM lifetime 

      Pouyan, Peyman; Amat Bertran, Esteve; Rubio Sola, Jose Antonio (2012)
      Comunicació de congrés
      Accés restringit per política de l'editorial
      The proactive reconfiguration is an emerging technique that enlarges the lifetime of memory systems with embedded SRAM cells. This work introduces a novel version that modifies and enhances the advantages of this technique ...

    • Process variability-aware proactive reconfiguration techniques for mitigating aging effects in nano scale SRAM lifetime 

      Rubio Sola, Jose Antonio; Amat Bertran, Esteve; Pouyan, Peyman (IEEE Press. Institute of Electrical and Electronics Engineers, 2012)
      Comunicació de congrés
      Accés restringit per política de l'editorial
      Process variations and device aging have a significant impact on the reliability and performance of nano scale integrated circuits. Proactive reconfiguration is an emerging technique to extend the lifetime of embedded ...

    • Reliability study on technology trends beyond 20nm 

      Amat Bertran, Esteve; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio (Lodz University of Technology, 2013)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      In this work, an assessment of different technology trends (planar CMOS, FinFET and III-V MOSFETs) has been carried out in front of some different reliability scenarios (variability and soft errors). The logic circuits ...

    • Resistive random access memory variability and its mitigation schemes 

      Pouman, Peyman; Amat Bertran, Esteve; Hamdioui, Said; Rubio Sola, Jose Antonio (2017-03-01)
      Article
      Accés restringit per política de l'editorial
      The need for design of new computing and storage paradigms has leaded to the emergence of new technologies and procedures. Among these technologies, emerging non-volatile memories such as RRAMs are getting intense attention ...

    • SET and noise fault tolerant circuit design techniques: application to 7 nm FinFET 

      Calomarde Palomino, Antonio; Amat Bertran, Esteve; Moll Echeto, Francisco de Borja; Vigara Campmany, Julio Enrique; Rubio Sola, Jose Antonio (2014-04-01)
      Article
      Accés obert
      In the near future of high component density and low-power technologies, soft errors occurring not only in memory systems and latches but also in the combinational parts of logic circuits will seriously affect the reliable ...

    • SRAM lifetime improvement by using adaptive proactive reconfiguration 

      Pouyan, Peyman; Amat Bertran, Esteve; Rubio Sola, Jose Antonio (IEEE Press. Institute of Electrical and Electronics Engineers, 2012)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Modern generations of CMOS technology nodes are facing critical causes of hardware reliability failures, which were not significant in the past. Such vulnerabilities make it essential to investigate new robust design ...

    • Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation 

      Rana, Manish; Canal Corretger, Ramon; Amat Bertran, Esteve; Rubio Sola, Jose Antonio (2017-03-01)
      Article
      Accés obert
      Bio-medical wearable devices restricted to their small-capacity embedded-battery require energy-efficiency of the highest order. However, minimum-energy point (MEP) at sub-threshold voltages is unattainable with SRAM memory, ...

    • Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation 

      Rana, Manish; Canal Corretger, Ramon; Amat Bertran, Esteve; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Text en actes de congrés
      Accés obert
      Bio-medical wearable devices restricted to their small-capacity embedded-battery require energy-efficiency of the highest order. However, minimum-energy point (MEP) at sub-threshold voltages is unattainable with SRAM memory, ...

    • Statistical Lifetime Analysis in Memristive Crossbar 

      Pouyan, Peyman; Amat Bertran, Esteve; Rubio Sola, Jose Antonio (2015)
      Text en actes de congrés
      Accés obert
      Emerging devices for future memory technologies have attracted great attention recently. Memristors are one of the most favorable such devices, due to their high scalability and compatibility with CMOS fabrication process. ...

    • Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm 

      Amat Bertran, Esteve; García Almudéver, Carmen; Aymerich, N.; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2014-10-01)
      Article
      Accés obert
      3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability as technology dimensions are reduced. In this work, we have shown that 22 nm ...

    • Systematic and random variability analysis of two different 6T-SRAM layout topologies 

      Amat Bertran, Esteve; Amatlle, E.; Gómez González, Sergio; Aymerich Capdevila, Nivard; García Almudéver, Carmen; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2013-09)
      Article
      Accés obert