Exploració per autor "Abella Ferrer, Jaume"
Ara es mostren els items 49-68 de 212
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Design of complex circuits using the via-configurable transistor array regular layout fabric
(IEEE Computer Society Publications, 2011)
Text en actes de congrés
Accés restringit per política de l'editorialLayout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new ... -
DIMP: A low-cost diversity metric based on circuit path analysis
(2017)
Text en actes de congrés
Accés obertDiversity has been regarded as a desirable property of redundant instances, since it allows circuits to behave differently in front of a given fault. However, while qualitatively diversity is a well-understood concept, ... -
DReAM: An approach to estimate per-Task DRAM energy in multicore systems
(2016-12)
Article
Accés obertAccurate per-task energy estimation in multicore systems would allow performing per-task energy-aware task scheduling and energy-aware billing in data centers, among other applications. Per-task energy estimation is ... -
DReAM: Per-task DRAM energy metering in multicore systems
(Springer, 2014)
Text en actes de congrés
Accés obertInteraction across applications in DRAM memory impacts its energy consumption. This paper makes the case for accurate per-task DRAM energy metering in multicores, which opens new paths to energy/performance optimizations, ... -
DTM: degraded test mode for fault-aware probabilistic timing analysis
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialExisting timing analysis techniques to derive Worst-Case Execution Time (WCET) estimates assume that hardware in the target platform (e.g., the CPU) is fault-free. Given the performance requirements increase in current ... -
Dynamic and execution views to improve validation, testing, and optimization of autonomous driving software
(Springer Nature, 2023-06)
Article
Accés obertThe adoption of autonomous driving (AD) software executed on high-performance multi-processor systems on chip (MPSoCs) contributes to increasing the overall system’s safety and efficiency. However, existing AD software ... -
Dynamic software randomisation: Lessons learnec from an aerospace case study
(2017-05-15)
Comunicació de congrés
Accés obertTiming Validation and Verification (V&V) is an important step in real-time system design, in which a system's timing behaviour is assessed via Worst Case Execution Time (WCET) estimation and scheduling analysis. For WCET ... -
Efficient cache architectures for reliable hybrid voltage operation using EDC codes
(2013)
Text en actes de congrés
Accés obertSemiconductor technology evolution enables the design of sensor-based battery-powered ultra-low-cost chips (e.g., below 1 p) required for new market segments such as body, urban life and environment monitoring. Caches have ... -
Empirical evidence for MPSoCs in critical systems: The case of NXP’s T2080 cache coherence
(IEEE, 2021)
Comunicació de congrés
Accés obertThe adoption of complex MPSoCs in critical real-time embedded systems mandates a detailed analysis their architecture to facilitate certification. This analysis is hindered by the lack of a thorough understanding of the ... -
En-route: on enabling resource usage testing for autonomous driving frameworks
(Association for Computing Machinery (ACM), 2020-03)
Text en actes de congrés
Accés obertSoftware resource usage testing, including execution time bounds and memory, is a mandatory validation step during the integration of safety-related real-time systems. However, the inherent complexity of Autonomous Driving ... -
Enabling unit testing of already-integrated AI software systems: The case of Apollo for autonomous driving
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Text en actes de congrés
Accés obertThe advanced AI-based software used for autonomous driving comprises multiple highly-coupled modules that are data and control dependent. Deploying those already-integrated software frameworks makes unit testing, a fundamental ... -
End-to-end QoS for the open source safety-relevant RISC-V SELENE platform
(arXiv, 2022)
Text en actes de congrés
Accés obertThis paper presents the end-to-end QoS approach to provide performance guarantees followed in the SELENEplatform, a high-performance RISC-V based heterogeneous SoC for safety-related real-time systems. Our QoS approach ... -
Energy efficient object detection for automotive applications with YOLOv3 and approximate hardware
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Text en actes de congrés
Accés obertDeep neural networks are the dominant models for perception tasks in the automotive domain, but their high computational complexity makes it difficult to execute them in real time with an acceptable power consumption on ... -
EOmesh: combined flow balancing and deterministic routing for reduced WCET estimates in embedded real-time systems
(2018-07-17)
Article
Accés obertThe increasing performance needs in critical real-time embedded systems (CRTES) can only be satisfied with the use of high-performance manycore processors. While NoC-based manycore systems are popular in the high-performance ... -
ePAPI: Performance Application ProgrammingInterface for Embedded Platforms
(2019)
Comunicació de congrés
Accés obertPerformance Monitoring Counters (PMCs) have been traditionally used in the mainstream computing domain to perform debugging and optimization of software performance. PMCs are increasingly considered in embedded time-critical ... -
EPC Enacted: Integration in an Industrial Toolbox and Use against a Railway Application
(Institute of Electrical and Electronics Engineers (IEEE), 2017-06-08)
Comunicació de congrés
Accés obertMeasurement-based timing analysis approaches are increasingly making their way into several industrial domains on account of their good cost-benefit ratio. The trustworthiness of those methods, however, suffers from the ... -
EPC: Extended Path Coverage for Measurement-Based Probabilistic Timing Analysis
(IEEE, 2016-01-18)
Comunicació de congrés
Accés obertMeasurement-based probabilistic timing analysis (MBPTA) computes trustworthy upper bounds to the execution time of software programs. MBPTA has the connotation, typical of measurement-based techniques, that the bounds ... -
Execution time distributions in embedded safety-critical systems using extreme value theory
(Inderscience, 2017)
Article
Accés obertSeveral techniques have been proposed to upper-bound the worst-case execution time behaviour of programs in the domain of critical real-time embedded systems. These computing systems have strong requirements regarding the ... -
Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study
(IEEE Computer Society Publications, 2011)
Comunicació de congrés
Accés restringit per política de l'editorialTime-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated ... -
Fitting processor architectures for measurement-based probabilistic timing analysis
(2016-11-01)
Article
Accés obertThe pressing market demand for competitive performance/cost ratios compels Critical Real-Time Embedded Systems industry to employ feature-rich hardware. The ensuing rise in hardware complexity however makes worst-case ...
