Exploració per autor "Abella Ferrer, Jaume"
Ara es mostren els items 37-56 de 212
-
Containing timing-related certification cost in automotive systems deploying complex hardware
(Association for Computing Machinery (ACM), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialMeasurement-Based Probabilistic Timing Analysis (MBPTA) techniques simplify deriving tight and trustworthy WCET estimates for industrial-size programs running on complex processors. MBPTA poses some requirements on the ... -
Contention in multicore hardware shared resources: Understanding of the state of the art
(Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2014)
Text en actes de congrés
Accés obertThe real-time systems community has over the years devoted considerable attention to the impact on execution timing that arises from contention on access to hardware shared resources. The relevance of this problem has been ... -
Contention tracking in GPU last-level cache
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertThe Last-level cache (LLC) is one of the main GPU’s shared resources that contributes to improve performance but also increases individual kernel’s performance variability. This is detrimental in scenarios in which some ... -
Contention-aware performance monitoring counter support for real-time MPSoCs
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Comunicació de congrés
Accés obertTasks running in MPSoCs experience contention delays when accessing MPSoC’s shared resources, complicating task timing analysis and deriving execution time bounds. Understanding the Actual Contention Delay (ACD) each task ... -
Control-flow recovery validation using microarchitectural invariants
(2011)
Text en actes de congrés
Accés restringit per política de l'editorialProcessors' design complexity increases with transistors' growing density. At the same time, market competence requires a decreasing time-to-market, and therefore, reduced validation time. Such time reduction imposes new ... -
Data bus slicing for contention-free multicore real-time memory systems
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertMemory access contention is one of the main contributors to tasks' execution time variability in real-Time multicores. Existing techniques to control memory contention based on time-sharing memory access do not scale well ... -
De-RISC – Dependable Real-Time Infrastructure for Safety-Critical Computer Systems
(Ada-Europe, 2020-06)
Article
Accés obertThe space domain demands increased performance, reliable and easy to verify and validate platforms tomatch the requirements of highly autonomous missions and systems that need to undergo qualification and certification ... -
De-RISC: A complete RISC-V based space-grade platform
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertThe H2020 EIC-FTI De-RISC project develops a RISC-V space-grade platform to jointly respond to several emerging, as well as longstanding needs in the space domain such as: (1) higher performance than that of monocore and ... -
De-RISC: the First RISC-V space-grade platform for safety-critical systems
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Text en actes de congrés
Accés obertThe increasing needs for performance in the space domain for highly autonomous systems calls for more powerful space MPSoCs and appropriate hypervisors to master them. These platforms must adhere to strict reliability, ... -
Deconstructing bus access control policies for real-time multicores
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialMulticores may satisfy the growing performance requirements of critical Real-Time systems which has made industry to consider them for future real-time systems. In a multicore, the bus contention-control policy plays a key ... -
Design and implementation of a fair credit-based bandwidth sharing scheme for buses
(Institute of Electrical and Electronics Engineers (IEEE), 2017-05-15)
Comunicació de congrés
Accés obertFair arbitration in the access to hardware shared resources is fundamental to obtain low worst-case execution time (WCET) estimates in the context of critical real-time systems, for which performance guarantees are essential. ... -
Design and integration of hierarchical-placement multi-level caches for real-Time systems
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés restringit per política de l'editorialEnabling timing analysis in the presence of caches has been pursued by the real-Time embedded systems (RTES) community for years due to cache's huge potential to reduce software's worst-case execution time (WCET). However, ... -
Design of complex circuits using the via-configurable transistor array regular layout fabric
(IEEE Computer Society Publications, 2011)
Text en actes de congrés
Accés restringit per política de l'editorialLayout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new ... -
DIMP: A low-cost diversity metric based on circuit path analysis
(2017)
Text en actes de congrés
Accés obertDiversity has been regarded as a desirable property of redundant instances, since it allows circuits to behave differently in front of a given fault. However, while qualitatively diversity is a well-understood concept, ... -
DReAM: An approach to estimate per-Task DRAM energy in multicore systems
(2016-12)
Article
Accés obertAccurate per-task energy estimation in multicore systems would allow performing per-task energy-aware task scheduling and energy-aware billing in data centers, among other applications. Per-task energy estimation is ... -
DReAM: Per-task DRAM energy metering in multicore systems
(Springer, 2014)
Text en actes de congrés
Accés obertInteraction across applications in DRAM memory impacts its energy consumption. This paper makes the case for accurate per-task DRAM energy metering in multicores, which opens new paths to energy/performance optimizations, ... -
DTM: degraded test mode for fault-aware probabilistic timing analysis
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialExisting timing analysis techniques to derive Worst-Case Execution Time (WCET) estimates assume that hardware in the target platform (e.g., the CPU) is fault-free. Given the performance requirements increase in current ... -
Dynamic and execution views to improve validation, testing, and optimization of autonomous driving software
(Springer Nature, 2023-06)
Article
Accés obertThe adoption of autonomous driving (AD) software executed on high-performance multi-processor systems on chip (MPSoCs) contributes to increasing the overall system’s safety and efficiency. However, existing AD software ... -
Dynamic software randomisation: Lessons learnec from an aerospace case study
(2017-05-15)
Comunicació de congrés
Accés obertTiming Validation and Verification (V&V) is an important step in real-time system design, in which a system's timing behaviour is assessed via Worst Case Execution Time (WCET) estimation and scheduling analysis. For WCET ... -
Efficient cache architectures for reliable hybrid voltage operation using EDC codes
(2013)
Text en actes de congrés
Accés obertSemiconductor technology evolution enables the design of sensor-based battery-powered ultra-low-cost chips (e.g., below 1 p) required for new market segments such as body, urban life and environment monitoring. Caches have ...
