Ara es mostren els items 30-49 de 212

    • Bus designs for time-probabilistic multicore processors 

      Jalle Ibarra, Javier; Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (European Interactive Digital Advertising Alliance (EDAA), 2014)
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      Probabilistic Timing Analysis (PTA) reduces the amount of information needed to provide tight WCET estimates in real-time systems with respect to classic timing analysis. PTA imposes new requirements on hardware design ...
    • Cache side-channel attacks and time-predictability in high-performance critical real-time systems 

      Trilla Rodríguez, David; Hernández Luz, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2018-06-24)
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      Embedded computers control an increasing number of systems directly interacting with humans, while also manage more and more personal or sensitive information. As a result, both safety and security are becoming ubiquitous ...
    • Characterizing fault propagation in safety-critical processor designs 

      Espinosa, Jaime; Hernandez, Carles; Abella Ferrer, Jaume (Institute of Electrical and Electronics Engineers (IEEE), 2015)
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      Achieving reduced time-to-market in modern electronic designs targeting safety critical applications is becoming very challenging, as these designs need to go through a certification step that introduces a non-negligible ...
    • CleanET: enabling timing validation for complex automotive systems 

      Vilardell Moreno, Sergi; Serra Mochales, Isabel; Tabani, Hamid; Abella Ferrer, Jaume; del Castillo Franquet, Joan; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2020)
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      Timing validation for automotive systems occurs in late integration stages when it is hard to control how the instances of software tasks overlap in time. To make things worse, in complex software systems, like those for ...
    • Compiler directed early register release 

      Jones, Timothy M.; O’Boyle, Michael F.P.; Abella Ferrer, Jaume; González Colás, Antonio María; Ergin, Oguz (Institute of Electrical and Electronics Engineers (IEEE), 2005)
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      This paper presents a novel compiler directed technique to reduce the register pressure and power of the register file by releasing registers early. The compiler identifies registers that mil only be read once and renames ...
    • Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration 

      Fernandez, Gabriel; Jalle, Javier; Abella Ferrer, Jaume; Quiñones, Eduardo; Vardanega, Tullio; Cazorla, Francisco J. (Institute of Electrical and Electronics Engineers (IEEE), 2016-10-11)
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      Numerous researchers have studied the contention that arises among tasks running in parallel on a multicore processor. Most of those studies seek to derive a tight and sound upper-bound for the worst-case delay with which ...
    • Computing worst-case contention delays for networks on chip 

      Cardona, Jordi; Hernandez, Carles; Abella Ferrer, Jaume (Barcelona Supercomputing Center, 2020-05)
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      Computing performance needs in domains such as automotive, avionics, railway, and space are on the rise. This is fueled by the trend towards implementing an increasing number of product functionalities in software that ...
    • Containing timing-related certification cost in automotive systems deploying complex hardware 

      Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Farrall, Glenn; Wartel, Franck; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2014)
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      Measurement-Based Probabilistic Timing Analysis (MBPTA) techniques simplify deriving tight and trustworthy WCET estimates for industrial-size programs running on complex processors. MBPTA poses some requirements on the ...
    • Contention in multicore hardware shared resources: Understanding of the state of the art 

      Fernández, Gabriel; Abella Ferrer, Jaume; Quiñones, Eduardo; Rochange, Christine; Vardanega, Tullio; Cazorla Almeida, Francisco Javier (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2014)
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      The real-time systems community has over the years devoted considerable attention to the impact on execution timing that arises from contention on access to hardware shared resources. The relevance of this problem has been ...
    • Contention tracking in GPU last-level cache 

      Barrera Herrera, Javier Enrique; Kosmidis, Leonidas; Tabani, Hamid; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2022)
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      The Last-level cache (LLC) is one of the main GPU’s shared resources that contributes to improve performance but also increases individual kernel’s performance variability. This is detrimental in scenarios in which some ...
    • Contention-aware performance monitoring counter support for real-time MPSoCs 

      Jalle Ibarra, Javier; Fernández, Mikel; Abella Ferrer, Jaume; Andersson, Jan; Patte, Mathieu; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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      Tasks running in MPSoCs experience contention delays when accessing MPSoC’s shared resources, complicating task timing analysis and deriving execution time bounds. Understanding the Actual Contention Delay (ACD) each task ...
    • Control-flow recovery validation using microarchitectural invariants 

      Carretero Casado, Javier Sebastián; Abella Ferrer, Jaume; Vera Gómez, Javier; Chaparro Valero, Pedro Alonso (2011)
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      Processors' design complexity increases with transistors' growing density. At the same time, market competence requires a decreasing time-to-market, and therefore, reduced validation time. Such time reduction imposes new ...
    • Data bus slicing for contention-free multicore real-time memory systems 

      Jalle Ibarra, Javier; Quiñones, Eduardo; Abella Ferrer, Jaume; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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      Memory access contention is one of the main contributors to tasks' execution time variability in real-Time multicores. Existing techniques to control memory contention based on time-sharing memory access do not scale well ...
    • De-RISC – Dependable Real-Time Infrastructure for Safety-Critical Computer Systems 

      Gómez, Francisco; Masmano, Miguel; Nicolau, Vicente; Andersson, Jan; Le Rhun, Jimmy; Trilla, David; Gallego, Felipe; Cabo, Guillem; Abella Ferrer, Jaume (Ada-Europe, 2020-06)
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      The space domain demands increased performance, reliable and easy to verify and validate platforms tomatch the requirements of highly autonomous missions and systems that need to undergo qualification and certification ...
    • De-RISC: A complete RISC-V based space-grade platform 

      Wessman, Nils-Johan; Malatesta, Fabio; Ribes, Stefano; Andersson, Jan; García Vilanova, Antonio; Masmano Tello, Miguel; Nicolau Gallego, Vicente; Gómez Molinero, Paco; Le Rhun, Jimmy; Alcaide Portet, Sergi; Cabo Pitarch, Guillem; Bas Jalón, Francisco; Benedicte Illescas, Pedro; Mazzocchetti, Fabio; Abella Ferrer, Jaume (Institute of Electrical and Electronics Engineers (IEEE), 2022)
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      The H2020 EIC-FTI De-RISC project develops a RISC-V space-grade platform to jointly respond to several emerging, as well as longstanding needs in the space domain such as: (1) higher performance than that of monocore and ...
    • De-RISC: the First RISC-V space-grade platform for safety-critical systems 

      Wessman, Nils-Johan; Malatesta, Fabio; Andersson, Jan; Gómez Molinero, Paco; Masmano Tello, Miguel; Nicolau Gallego, Vicente; Le Rhun, Jimmy; Cabo Pitarch, Guillem; Bas Jalón, Francisco; Lorenzo Ortega, Rubén; Sala Sucarrats, Oriol; Trilla Rodríguez, David; Abella Ferrer, Jaume (Institute of Electrical and Electronics Engineers (IEEE), 2021)
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      The increasing needs for performance in the space domain for highly autonomous systems calls for more powerful space MPSoCs and appropriate hypervisors to master them. These platforms must adhere to strict reliability, ...
    • Deconstructing bus access control policies for real-time multicores 

      Jalle Ibarra, Javier; Abella Ferrer, Jaume; Quiñones, Eduardo; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2013)
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      Multicores may satisfy the growing performance requirements of critical Real-Time systems which has made industry to consider them for future real-time systems. In a multicore, the bus contention-control policy plays a key ...
    • Design and implementation of a fair credit-based bandwidth sharing scheme for buses 

      Slijepcevic, Mladen; Hernandez, Carles; Abella Ferrer, Jaume; Cazorla, Francisco J. (Institute of Electrical and Electronics Engineers (IEEE), 2017-05-15)
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      Fair arbitration in the access to hardware shared resources is fundamental to obtain low worst-case execution time (WCET) estimates in the context of critical real-time systems, for which performance guarantees are essential. ...
    • Design and integration of hierarchical-placement multi-level caches for real-Time systems 

      Benedicte Illescas, Pedro; Hernandez, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2018)
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      Enabling timing analysis in the presence of caches has been pursued by the real-Time embedded systems (RTES) community for years due to cache's huge potential to reduce software's worst-case execution time (WCET). However, ...
    • Design of complex circuits using the via-configurable transistor array regular layout fabric 

      Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society Publications, 2011)
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      Layout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new ...