Now showing items 1-20 of 68

  • A large-scale spiking neural networks emulation architecture 

    Pirrone, Vito (Universitat Politècnica de Catalunya, 2014-09-09)
    Master thesis
    Open Access
    The purpose of this work is to design a new version (called SNAVA+) of the architecture SNAVA, an SNN hardware emulator implemented on a XilinX Kintex-7 FPGA. SNAVA+ increases the capabilities of SNAVA in order to have a ...
  • AMC: Advanced Multi-accelerator Controller 

    Hussain, Tassadaq; Haider, Amna; Gursal, Shakaib A.; Ayguadé Parra, Eduard (2015-01)
    Article
    Restricted access - publisher's policy
    The rapid advancement, use of diverse architectural features and introduction of High Level Synthesis (HLS) tools in FPGA technology have enhanced the capacity of data-level parallelism on a chip. A generic FPGA based HLS ...
  • An LMS-based adaptive predistorter for cancelling nonlinear memory effects in RF power amplifiers 

    Montoro López, Gabriel; Gilabert Pinal, Pere Lluís; Bertran Albertí, Eduardo; Cesari Bohigas, Albert; García, José Antonio (2007-12)
    Conference lecture
    Open Access
    This paper presents the design of an adaptive Digital Predistorter (DPD) for Power Amplifier (PA) linearization whoseimplementation and real time adaptation can be fully performed in a Field Programmable Gate Array (FPGA). ...
  • An Optical Burst Switching Control Plane Architecture and its Implementation 

    Triay Marquès, Joan; Rubio, Jesús; Cervelló Pastor, Cristina (2006-09-18)
    Conference lecture
    Open Access
    This paper proposes a new design and implementation of a control plane for Optical Burst Switched networks. The design is based on the principles of generality, transparency, portability and efficiency. In this way, the ...
  • Analog Signal Adquisition and FFT Application for a Linux Embeded System Lab 

    Montes O'connor, Carlos Jesús (Universitat Politècnica de Catalunya, 2014-05)
    Master thesis (pre-Bologna period)
    Open Access
    [ANGLÈS] The project goal is to design a platform based on an existing HW/SW embeded Linux system containing a FPGA, within an academic environment. To accomplish that objective, a specific application for signal Adquisition ...
  • Análisis de una aplicación de "Pattern Matching" en una FPGA 

    Trueba Calero, Ariadna (Universitat Politècnica de Catalunya, 2008-06-20)
    Master thesis (pre-Bologna period)
    Open Access
  • Aplicació de la lògica difusa a un algoritme LMS en un entorn FPGA 

    Pertegal Miranda, David (Universitat Politècnica de Catalunya, 2008-11-12)
    Master thesis (pre-Bologna period)
    Open Access
    Aquest treball fi de carrera presenta el disseny i desenvolupament d’un algoritme de lògica difusa que té per objectiu millorar l’adaptació d’un sistema de linealització basat en tècniques de predistorsió (PD) digital. Aquest ...
  • Beehive: an FPGA-based multiprocessor architecture 

    Arcas Abella, Oriol (Universitat Politècnica de Catalunya, 2009-09-23)
    Master thesis
    Open Access
    In recent years, to accomplish with the Moore's law hardware and software designers are tending progressively to focus their efforts on exploiting instruction-level parallelism. Software simulation has been essential for ...
  • Bioinspired onset detection using snava architecture 

    Sekar, Sanjana (Universitat Politècnica de Catalunya, 2014-06-06)
    Master thesis (pre-Bologna period)
    Open Access
    [ANGLÈS] The main objective of this project is to develop an application which is biologically inspired from one of the functionalities of the human ear and is implemented on a neuromorphic architecture called SNAVA. The ...
  • Bit error rate test for optical communication link using prbs generated by an fpga - hardware implementation 

    Varagur Karthikeyan, Sadhvi (Universitat Politècnica de Catalunya, 2014-06-06)
    Master thesis (pre-Bologna period)
    Open Access
    The Objective involved realizing a PRBS-BERT to analyze the optical link performance. The configuration of the board for the application involved studying the daughter board, the interconnect (i.e. HSMC) and thereby ...
  • Bit error rate test for optical communication link using prbs generated by an fpga - system design 

    Vairavel, Sindhu (Universitat Politècnica de Catalunya, 2014-06-06)
    Master thesis (pre-Bologna period)
    Open Access
    Bit Error Rate Testing(BERT) was implemented using Cyclone III FPGA Starter Kit along with THDB_ADA board and interfaced with several kilometers long optical fiber, to study the link performance of the optical communication ...
  • Co-diseño hardware-software de una unidad en coma flotante para microprocesador de 32 bits 

    Lumbiarres López, Rubén (Universitat Politècnica de Catalunya, 2008-06)
    Master thesis (pre-Bologna period)
    Open Access
    El uso de números en coma flotante es muy habitual en la programación software para la resolución de todo tipo de algoritmos. Dada la particular forma de codificar valores en este formato, definida en la norma IEEE 754, ...
  • Compilación C a VHDL de códigos de bucles con reuso de datos 

    Sánchez Fernández, Raúl (Universitat Politècnica de Catalunya, 2010-03-25)
    Master thesis (pre-Bologna period)
    Open Access
    Durante este proyecto se ha desarrollado un compilador fuente a fuente, de nombre CtoVHDL, capaz de traducir bucles de C a VHDL. Con esta traducción se crea un acelerador hardware capaz de ejecutar el bucle en una FPGA. ...
  • Comunicación y procesado de datos entre un ordenador y una FPGA 

    Padilla Segovia, Xavier (Universitat Politècnica de Catalunya, 2015-10-15)
    Master thesis
    Restricted access - confidentiality agreement
    A digital system which makes the communication between a computer and the evaluation board DE2 from Altera. It also makes a data processing of a parametric hardware implemented inside the FPGA.
  • Cooperative communication to minimize the outage probability in a hard real-time scenario 

    Cuenca Gil, David (Universitat Politècnica de Catalunya, 2012-01-06)
    Bachelor thesis
    Restricted access - author's decision
    Cooperative communication is one of the most recent techniques to improve the performance in wireless networks, in terms of increasing the throughput or improving the reliability. It consists in using some of the nodes ...
  • Desarrollo de una plataforma de trabajo para la investigación 

    Blázquez Francisco, Víctor (Universitat Politècnica de Catalunya, 2010-06-22)
    Master thesis (pre-Bologna period)
    Open Access
  • Desenvolupament en una FPGA d'un transmissor basat en una arquitectura LINC: 

    Reyes Navarro, Carlos Alberto (Universitat Politècnica de Catalunya, 2010-07-23)
    Bachelor thesis
    Open Access
  • Design and implementation of a low-cost FPGA-Based bioimpedance measurement system 

    González Gutiérrez, Miguel (Universitat Politècnica de Catalunya, 2014-10-24)
    Master thesis
    Open Access
    Currently, many impedance measurement systems have been developed. This project details the design, implementation and characterization of a FPGA-based bioimpedance measurement system, whose goal is obtaining good performance ...
  • Design and implementation of an ARMv4 tightly coupled multicore in VHDL and validation on a FPGA 

    Ariño Alegre, Carlos (Universitat Politècnica de Catalunya / Technische Universität Berlin, 2012-07-09)
    Master thesis (pre-Bologna period)
    Open Access
    [ANGLÈS] On one hand, few years ago increasing the clock speed was the preferred tactic by manufacturers to gradually increase the performance of computers. However, from certain speeds there are some limitations. Some ...
  • Design, implementation, and verification of an FPGA-based control system for a permanent-magnet motor drive built upon a three-phase four-level active-clamped inverter 

    García Rojas, Gabriel (Universitat Politècnica de Catalunya, 2015-05)
    Master thesis
    60 months embargo
    [ANGLÈS] The present work summarizes the work and knowledge acquired by the author during its Master’s Thesis in the Research Group in Power Electronics, GREP. The development is based on the Multilevel Active-Clamped (MAC) ...