• RVC: A mechanism for time-analyzable real-time processors with faulty caches 

    Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Sazeides, Yanos; Valero Cortés, Mateo (2011)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Geometry scaling due to technology evolution as well as Vcc scaling lead to failures in large SRAM arrays such as caches. Faulty bits can be tolerated from the average performance perspective, but make critical realtime ...
  • Using randomized caches in probabilistic real-time systems 

    Quiñones, Eduardo; Berger, Emery D.; Bernat, Guillem; Cazorla Almeida, Francisco Javier (2009)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    While hardware caches are generally effective at improving application performance, they greatly complicate performance prediction. Slight changes in memory layout or data access patterns can lead to large and ...