Ara es mostren els items 29-43 de 43

  • Probabilistic timing analysis on conventional cache designs 

    Kosmidis, Leonidas; Curtsinger, Charlie; Quiñones Moreno, Eduardo; Abella Ferrer, Jaume; Berger, Emery D.; Cazorla Almeida, Francisco Javier (2013)
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    Probabilistic timing analysis (PTA), a promising alternative to traditional worst-case execution time (WCET) analyses, enables pairing time bounds (named probabilistic WCET or pWCET) with an exceedance probability (e.g., ...
  • Probabilistically time-analyzable complex processors in hard real- time systems 

    Slijepcevic, Mladen; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Barcelona Supercomputing Center, 2015-05-05)
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    Critical Real-Time Embedded Systems (CRTES) feature performance-demanding functionality. High-performance hardware and complex software can provide such functionality, but the use of aggressive technology challenges ...
  • RunPar: An allocation algorithm for automotive applications exploiting runnable parallelism in multicores 

    Panic, Milos; Kehr, Sebastian; Quiñones Moreno, Eduardo; Boddecker, Bert; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2014)
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    Automotive applications increasingly rely on AUTOSAR for their design and execution. AUTOSAR applications comprise functions, called runnables, that are grouped into AUTOSAR tasks. Tasks are the unit of scheduling (UoS) ...
  • RVC: A mechanism for time-analyzable real-time processors with faulty caches 

    Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Sazeides, Yanos; Valero Cortés, Mateo (2011)
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    Geometry scaling due to technology evolution as well as Vcc scaling lead to failures in large SRAM arrays such as caches. Faulty bits can be tolerated from the average performance perspective, but make critical realtime ...
  • Selective replication: a lightweight technique for soft errors 

    Vera, Xavier; Abella Ferrer, Jaume; Carretero Casado, Javier Sebastián; González Colás, Antonio María (ACM Press. Association for Computing Machinery, 2009-12)
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    Soft errors are an important challenge in contemporary microprocessors. Modern processors have caches and large memory arrays protected by parity or error detection and correction codes. However, today’s failure rate is ...
  • Sensible energy accounting with abstract metering for multicore systems 

    Liu, Qixiao; Moreto Planas, Miquel; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier; Jiménez, Daniel A.; Valero Cortés, Mateo (2016-01)
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    Chip multicore processors (CMPs) are the preferred processing platform across different domains such as data centers, real-time systems, and mobile devices. In all those domains, energy is arguably the most expensive ...
  • Software directed issue queue power reduction 

    Jones, Timothy M.; O’Boyle, Michael F.P.; Abella Ferrer, Jaume; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2005)
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    The issue logic of a superscalar processor dissipates a large amount of static and dynamic power. Furthermore, its power density makes it a hot-spot requiring expensive cooling systems and additional packaging. In this ...
  • TASA: toolchain-agnostic static software randomisation for critical real-time systems 

    Kosmidis, Leonidas; Vargas, Roberto; Morales, David; Quiñones Moreno, Eduardo; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2016)
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    Measurement-Based Probabilistic Timing Analysis (MBPTA) derives WCET estimates for tasks running on processors comprising high-performance features such as caches. MBPTA's correct application requires the system to exhibit ...
  • The next convergence: High-performance and mission-critical markets 

    Girbal, Sylvain; Moreto Planas, Miquel; Grasset, Arnaud; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier; Yehia, Sami (2013)
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    The well-known convergence of the high-performance computing and the mobile markets has been a dominating factor in the computing market during the last two decades. In this paper we witness a new type of convergence between ...
  • Time-analysable non-partitioned shared caches for real-time multicore systems 

    Slijepcevic, Mladen; Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2014)
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    Shared caches in multicores challenge Worst-Case Execution Time (WCET) estimation due to inter-task interferences. Hard-ware and software cache partitioning address this issue although they complicate data sharing among ...
  • Timing verification of fault-tolerant chips for safety-critical applications in harsh environments 

    Slijepcevic, Mladen; Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Cazorla, Francisco J. (2014-11-01)
    Article
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    Critical real-time embedded systems feature complex safety-related, performance-demanding functionality. High-performance hardware and software can provide such functionality, but the use of aggressive technologies and ...
  • Validating the reliability of WCET estimates with MBPTA 

    Milutinovic, Suzana; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Barcelona Supercomputing Center, 2015-05-05)
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    Estimating the worst-case execution time (WCET) of tasks in a system is an important step in timing verification of critical real-time embedded systems. Measurement-Based Probabilistic Timing Analysis (MBPTA) is a novel ...
  • Variations-aware circuit designs for microprocessors 

    Pons Solé, Marc; Moll Echeto, Francisco de Borja; Abella Ferrer, Jaume (2010)
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    A new trend that is becoming dominant is to improve layout regularity so that the layouts to be printed are more repetitive and easy to manufacture. Our proposal is to push to the limit layout regularity to minimize ...
  • VCTA: A Via-Configurable Transistor Array regular fabric 

    Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society Publications, 2010)
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    Layout regularity is introduced progressively by integrated circuit manufacturers to reduce the increasing systematic process variations in the deep sub-micron era. In this paper we focus on a scenario where layout regularity ...
  • Via-configurable transistor array: a regular design technique to improve ICs yield 

    Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio, Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (2007-09)
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    Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That is why regular techniques with different degrees of regularity are emerging as possible solutions. Our ...