Now showing items 1-2 of 2

  • Hybrid transactional memory with pessimistic concurrency control 

    Vallejo, Enrique; Sanyal, Sutirtha; Harris, Tim; Vallejo, Fernando; Beivide, Ramón; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2011-06)
    Restricted access - publisher's policy
    Transactional Memory (TM) intends to simplify the design and implementation of the shared-memory data structures used in parallel software. Many Software TM systems are based on writer-locks to protect the data being ...
  • Light NUCA: a proposal for bridging the inter-cache latency gap 

    Suárez, Dario; Monreal Arnal, Teresa; Vallejo, Fernando; Beivide Palacio, Julio Ramón; Viñals Yufera, Víctor (IEEE Computer Society, 2009)
    Conference lecture
    Open Access
    To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between them and fast L1 caches (inter-cache latency gap). ...