• Architectural exploration of large-scale hierarchical chip multiprocessors 

    Nikitin, Nikita; San Pedro Martín, Javier de; Cortadella Fortuny, Jordi (2013)
    Article
    Accés restringit per política de l'editorial
    The continuous scaling of nanoelectronics is increasing the complexity of chip multiprocessors (CMPs) and exacerbating the memory wall problem. As CMPs become more complex, the memory subsystem is organized into more ...
  • Automatic synthesis and optimization of chip multiprocessors 

    Nikitin, Nikita (Universitat Politècnica de Catalunya, 2013-04-05)
    Tesi
    Accés obert
    The microprocessor technology has experienced an enormous growth during the last decades. Rapid downscale of the CMOS technology has led to higher operating frequencies and performance densities, facing the fundamental ...
  • Physical planning for the architectural exploration of large-scale chip multiprocessors 

    San Pedro Martín, Javier de; Nikitin, Nikita; Cortadella Fortuny, Jordi; Petit Silvestre, Jordi (2013)
    Comunicació de congrés
    Accés restringit per política de l'editorial
    This paper presents an integrated flow for architectural exploration and physical planning of large-scale hierarchical tiled CMPs. Classical floorplanning and wire planning techniques have been adapted to incorporate layout ...
  • Physical-aware system-level design for tiled hierarchical chip multiprocessors 

    Cortadella Fortuny, Jordi; San Pedro Martín, Javier de; Nikitin, Nikita; Petit Silvestre, Jordi (ACM Press. Association for Computing Machinery, 2013)
    Text en actes de congrés
    Accés obert
    Tiled hierarchical architectures for Chip Multiprocessors (CMPs) represent a rapid way of building scalable and power-e fficient many-core computing systems. At the early stages of the design of a CMP, physical parameters ...
  • Static task mapping for tiled chip multiprocessors with multiple voltage islands 

    Nikitin, Nikita; Cortadella Fortuny, Jordi (Springer Verlag, 2012)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    The complexity of large Chip Multiprocessors (CMP) makes design reuse a practical approach to reduce the manufacturing and design cost of high-performance systems. This paper proposes techniques for static task mapping ...
  • Static task mapping for tiled chip multiprocessors with multiple voltage islands 

    Nikitin, Nikita; Cortadella Fortuny, Jordi (2011)
    Report de recerca
    Accés obert
    The complexity of large Chip Multiprocessors (CMP) makes design reuse a practical approach to reduce the manufacturing and design cost of high-performance systems. This paper proposes techniques for static task mapping ...